depletion-layer transistor [电子] 耗尽层型晶体管
four layer transistor 四层晶体管
four-layer transistor [电子] 四层晶体管
depletion layer transistor 耗尽层型晶体管
In addition, the buffer layer can mitigate parallel conduction issues between transistor devices and the silicon substrate.
此外,缓冲层可以减少晶体管之间的设备和硅衬底平行的传导问题。
We try to obtain the common-base current gain a of the parasitic PNP transistor from the eloping profile of the collector region including the effect of buried-layer.
本文从包括埋层影响的集区杂质分布出发,求出了寄生PNP晶体管的共基极电流放大系数。
In one embodiment, a thin film transistor comprises a layer of the organic semiconductor material.
在一个实施方案中,薄膜晶体管包含有机半导体材料层。
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