An approach for analyzing coupling rc interconnect delay based on "effective capacitance" is presented.
基于“有效电容”的概念提出了一种分析两相邻耦合r C互连延时的方法。
This paper makes a deep research and discussion for crosstalk noise and interconnect delay combined the interconnect lines characteristic in nanometer process.
本文结合纳米级工艺下互连线特性，对互连串扰噪声与延时的相关问题进入了深入的研究探讨。
Based on the theory of the probability interpretation algorithm, a statistical model of RLC interconnect delay in the presence of process variations was put forward.
基于概率解释算法的原理，提出了一种考虑工艺波动的RLC互连延时统计模型，该模型使用了对数正态分布函数。
This paper presented an innovative analytical delay model for RLC interconnects utilized in the estimation of interconnect delay for deep submicrometer VLSI circuits.
提出了用来评估深亚微米vlsi电路中rlc互连延时的一种新的解析延时模型。
Considering interconnect delay in early design stages is a hot spot and how to establish an interconnect-centered synthesis method is a hard task, yet without mature approaches.
在前期设计阶段考虑互连延迟问题已是当前研究的重要课题。建立以互连为中心的综合方法是当前的一个棘手问题，尚未有成熟的方法。
Interconnect wire delay is a very important question that must to be resolved in deep submicron IC design.
深亚微米集成电路的互连线延迟是设计中需十分重视并必须解决的问题。
In the case of FPGAs, the number of blocks used will also greatly influence the final delay after routing because most of the delays is the wiring delays due to the programmable interconnect existed.
在FPGA的情况下，所使用的元胞块数量也会在很大程度上影响布线后的最终延迟，因为大多数延迟是由存在的可编程互连所引起的布线延迟。
The factors that affect the interconnect wire delay and the resolution ways from to lower the signal swing and change switch threshold value aspect are described in this paper.
本文讨论了影响互连线延迟的因素，并讨论了从降低信号摆幅、改变开关阈值方面解决延迟、功耗等问题。
In this thesis, the interconnect model in the SOC design, and the delay, power and design method for layout design are investigated from the perspective of interconnect design.
本文主要针对SOC中的连线模型以及从连线设计角度对版图设计中的时延、功耗以及设计方法进行研究。
Introduced in this paper is a new approach for VLSI interconnect global routing that can optimize both congestion and delay, due to routing topology flexibilities.
文章介绍了一个可以同时考虑时延约束和拥塞度优化的VLSI总体布线新方法。
Introduced in this paper is a new approach for VLSI interconnect global routing that can optimize both congestion and delay, due to routing topology flexibilities.
文章介绍了一个可以同时考虑时延约束和拥塞度优化的VLSI总体布线新方法。
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