RS hardware decoder can be used in the ground receiver system.
R S码硬件译码器也可应用于地面接收系统中。
This paper introduces a hardware design of two dimensional product code iterative decoder.
介绍了一种乘积码迭代译码器的硬件设计方案。
Taking Motorola Dragon Ball MC68EZ328 processor as the hardware platform and on the basis of MIDI file decoder and PWM driver, MIDI music player has designed and realized.
以基于摩托罗拉龙珠mc68ez328处理器的嵌入式开发板为硬件平台，在MIDI文件解码器和PWM驱动程序的基础上，设计并实现了MIDI音乐播放器。
This Viterbi decoder has low latency, efficient memory organization, and low hardware complexity compared with other Viterbi decoders using traditional trace-back methods.
与采用传统回溯法的译码器相比，该译码器具有较低的译码时延、有效的存储空间管理和较低的硬件复杂度。
With a 16-bit internal hardware counter, the decoder is feasible for interfacing encoder and CPU in the development of multi-axis closed-loop movement control system.
解码器内部具有16位硬件计数器，与CPU接口方便，非常适合于多轴闭环运动控制系统的开发。
Then it mainly discusses the hardware design of the key unit in LDPC decoder-check functional unit.
紧接着讨论了LDPC译码器中的核心运算单元一校验功能单元的硬件设计。
ST Application programming Interface-STAPI drives the underlying hardware, video and audio decoder and display devices, and provides the upper software easy programming interface.
ST应用程序接口-STAPI负责底层硬件视音频解码和显示的驱动，并向上层软件提供良好的编程接口。
The encoder and decoder is optimized for high-speed modern communications technology, particularly in the higher hardware resources environment.
该编码器和译码器适合用于高速率的现代通信技术，特别是硬件资源较丰富的环境。
The architecture of video decoder is transforming from dedicated hardware to HW/SW partition owing to the powerful process of hardware and the flexibility and programmability of software.
视频解码芯片的结构因硬件强大的处理能力和软件灵活的可编程功能从硬件转向软硬件分区结构。
Because the decoding complexity of H. 264 is very high, software implementation can't decode in real time. The decoder must be implemented in hardware.
由于H . 264的解码复杂度很高，软件实现难以满足实时性的要求，所以需要采用硬件解码。
The PCGC decoder has good performance, but its high computation complexity interferes with its hardware implement.
这种译码算法的性能较好，但运算复杂度高，不利于硬件实现。
This paper introduces a method of hardware implementation in channel decoding, giving an emphasis on the decoding of punctured code and synchronization module following Viterbi decoder.
文中提出了信道译码硬件实现的一种方案，解决了其中删节码的解码和Viterbi译码后同步等难题。
With the development of LDPC algorithm which has a hardware-friendly trend, the VLSI realization of LDPC decoder is becoming ever the focus of researchers.
随着LDPC译码算法领域的研究日趋成熟和越来越易于硬件实现的发展趋势，LDPC译码器的VLSI实现才逐渐成为研究者关注的焦点。
This is a sound came to through the Morse code decoder decoding a text, no additional hardware, you only need a computer with a sound card and a receiver.
这是一个把通过声卡传来的摩尔斯式电码代码解码成文字的解码器，无需额外硬件，你只需要一台带声卡的计算机和一台接收机。
Hardware implementation results show that the resource efficiency of the multi-rate decoder is much better than that of traditional single-rate decoders.
硬件实现结果表明，该译码器的资源利用率远远超过了传统的单码率译码器。
Hardware implementation results show that the resource efficiency of the multi-rate decoder is much better than that of traditional single-rate decoders.
硬件实现结果表明，该译码器的资源利用率远远超过了传统的单码率译码器。
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