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RS hardware decoder can be used in the ground receiver system.
R S码硬件译码器也可应用于地面接收系统中。
This paper introduces a hardware design of two dimensional product code iterative decoder.
介绍了一种乘积码迭代译码器的硬件设计方案。
This Viterbi decoder has low latency, efficient memory organization, and low hardware complexity compared with other Viterbi decoders using traditional trace-back methods.
与采用传统回溯法的译码器相比，该译码器具有较低的译码时延、有效的存储空间管理和较低的硬件复杂度。
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