The gate region was fabricated by V-groove and Al sputtering, which can simplify the process, and make devices flexible in the adjustment process.
使用V形槽工艺，用溅射铝的方法代替扩硼工艺制备静电感应晶体管的栅极区，简化了工艺流程，使器件在调试过程中具有很大灵活性。
The MOSFET input diode is controlled by an electric field in the gate region, thus the input impedance is always extremely high because there is no forward biased diode to lower the input impedance.
MOSFET的输入二极管是由一个电场控制在门区，因此总是输入阻抗非常高，因为没有正向偏置二极管，以降低输入阻抗。
In particular, as a non-volatile memory device undergoes many programming cycles, charge becomes trapped in the insulator or dielectric between the floating gate and the channel region.
特定来说，在非易失性存储器装置经历许多编程循环时，电荷变为俘获在浮动栅极与沟道区之间的绝缘体或电介质中。
Before baby's, in gate does not have the ossein protection region, under the scalp is the brain organization.
宝宝的前in门是没有骨质保护的区域，头皮下就是脑组织。
The switching element may be formed on the insulating substrate in a pixel region defined by gate and data lines adjacent to each other.
开关元件可以形成于像素区域中的绝缘衬底上，像素区域由彼此相邻的栅极线和数据线限定。
The resistive memory cell comprises a first gate, a second gate, a common doped region, a contact plug, a bit line and a resistive memory element.
所述电阻式存储器单元包括第一栅极、第二栅极、共用掺杂区域、接触窗插塞、位线以及电阻式存储器元件。
Furthermore, the common doped region of the first gate and the second gate is disposed in the substrate.
此外，第一栅极与第二栅极的共用掺杂区域配置于基底中。
The DRAM further has a floating gate insulated from the surface and is positioned between the first region and the second region.
所述DRAM进一步包括与所述表面绝缘的浮栅，且位于所述第一区域和 所述第二区域之间。
The body region was doped high to increase the back gate threshold voltage.
增加体区掺杂，以提高背栅阈值电压；
A control gate having a thin gate oxide film is formed over a center channel portion of the channel region.
在沟道区的中央沟道部分上形成具有薄的栅氧化物膜的控制栅。
The transistor may include a gate structure, a source region, and a drain region.
晶体管包含一栅结构、一源区和一漏区。
A source region and a drain region are formed in the fin at the opposite sides of the gate electrode.
源区和漏区形成在鳍部内栅极的相对侧处。
The semiconductor device further has a trench gate (32) facing a portion of the intermediate region via an insulating layer (33).
所述半导体器件还包括沟槽栅极(32)，其通过绝缘层(33)面对部分所述中间区。
The semiconductor device further has a trench gate (32) facing a portion of the intermediate region via an insulating layer (33).
所述半导体器件还包括沟槽栅极(32)，其通过绝缘层(33)面对部分所述中间区。
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