绝不要依靠门延迟。
Then, CL-ACL structure is improved, simulation and verification under real gate delay is done.
改进了互补逻辑—交替互补逻辑(CL - ACL)结构，并做了考虑门级延迟的模拟验证。
Real time graphic display of probe position, beam surface position, gate delay and gate width during scanning.
实时显示探针位置所对应的图形，播送表面位置，门控和门控宽度。
Always use fully synchronous design. You never need to reply on gate delay if your design is fully synchronous.
始终使用完全同步设计。如果设计是全同步的，则无需回应门延迟。
Experimental results with the less design time, area reductions of up to 48% and gate delay reduction of 40% demonstrate the effectiveness of the approach.
实践结果显示设计时间缩短、硬核性能得到提高，面积缩小48%，门延时缩短40%。
Both coarse count and fine count which base on the clock and gate delay separately were used to quantify them. Thus, time variable were converted into digital variable.
采用基于门延时的精细计数来量化被测时间间隔中与时钟不同步的部分，这样时间量就被转换成了数字量。
Static timing analysis is widely applied in timing verification because of its high speed and great capacity. The gate delay computing is a critical part of static timing analysis.
静态时序分析由于速度快和容量大而广泛应用于时序验证，而门延时的计算则是静态时序分析中的关键部分。
Due to the subtle error among different manufacturing equipment, the gate delay of circuits is different and varies in a given scope, which induces the time uncertainty of the waveform.
由于制造设备本身存在微小误差，具体门的延时并不相同，而是在一定范围内变化，引起波形变化的时间不确定。
The schottky diode bypasses the gate resistor in the gate discharge path, so that there is no falling edge delay. The delay at the rising edge adds dead time.
为了增加更多的死区时间，补偿功率管的切换瞬间短暂延时，增加了一个肖特基二极管，与栅极电阻。
AN artificial delay line which was designed by using the DYL integrated linear AND-OR gate created first in China were proposed.
本文提出了一种用我国首创的DY L集成线性“与或”门设计成的模拟延迟线。
Low resistivity of gate line is very useful for large size panel by overcoming rc delay, also, for small size application with fine pitch process.
为克服大尺寸显示面板中反应时间的延迟问题，采用低阻栅线是十分有益的，同样在小尺寸面板上也存在这种相互匹配的过程。
The shooting delay time as result of the equipped shooting gate is studied for the weapon system with shooting gate.
针对具有射击门体制的武器系统，研究其因加入射击门而产生的射击延时。
A new digital beam forming (DBF) method is proposed. It combines the parallel delay LMS (PDLMS) algorithm and the field programmable gate array (FPGA).
采用高并行度的并行延时最小均方(PDLMS)算法，用现场可编程门阵列(FPGA)实现自适应数字波束形成模块。
The results show that, in the tubular pump start the process, the delay time of opening gate and the speed of the starting gate are significant influence the transition process.
计算结果显示，在贯流泵站起动过程中，闸门开启延时时间以及闸门开启速度对起动过渡过程均有明显影响。
This paper proposes a new gate drive method for active clamped quasi resonant converters. Instead of a digital delay circuit, only a resistor and a diode are added to produce correct drive waveforms.
提出了有源钳位准谐振变换器的一种新的驱动方式，它无需经过数字电路延时，只需一个电阻和二极管构成的小网络。
Additional features include: programmable transition delay, low quiescent current, higher efficiency at light loads, and high speed control to quickly turn off both gate drivers.
其它附加功能包括：可编程跳变延时、低静态电流、在轻载时提供更高的效率，以及快速关断两个驱动器的高速控制。
This paper puts forward a method of using CMOS chip of delay and ECL gate to generate short pulse, and analyzes the principle of generation.
提出了使用延时芯片和ECL门产生极窄脉冲的方法，并对其产生原理做了理论分析。
The circuit is based on a simple XNOR logic gate and delay lines to sample the output of the XNOR gate, so very little area is introduced.
该电路建立在一个简单的异或非逻辑门和延迟线的基础上，通过抽样调查异或非门的输出来检测电路的错误点，引入的多余面积很少。
In spite of the fact that de-icing fluid had been applied at the gate, a departure delay after the aircraft taxied on to the runway allowed ice to re-form on the wings, leading to the crash.
NTSB在报告中得出结论认为，飞机坠毁是由飞机刚起飞后机翼结冰引起的。尽管在登机口已经喷洒了除冰液，但经过飞机在跑道上的滑行，加上起飞延迟，机翼重新结冰，导致了此次坠机事故。
The dynamic performance of the gates and the advantages of internal structure of tri-state gate control are also presented. Results of the averaged time delay design are given. which have bee...
同时介绍了该分频器各级门的动态特性以及内部用三态门控制结构的优点，给出了平均延迟时间的设计结果，该设计已应用于高频时钟芯片的大批量生产中。
The dynamic performance of the gates and the advantages of internal structure of tri-state gate control are also presented. Results of the averaged time delay design are given. which have bee...
同时介绍了该分频器各级门的动态特性以及内部用三态门控制结构的优点，给出了平均延迟时间的设计结果，该设计已应用于高频时钟芯片的大批量生产中。
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