Static timing analysis is widely applied in timing verification because of its high speed and great capacity. The gate delay computing is a critical part of static timing analysis.
静态时序分析由于速度快和容量大而广泛应用于时序验证，而门延时的计算则是静态时序分析中的关键部分。
Then, CL-ACL structure is improved, simulation and verification under real gate delay is done.
改进了互补逻辑—交替互补逻辑(CL - ACL)结构，并做了考虑门级延迟的模拟验证。
Due to the subtle error among different manufacturing equipment, the gate delay of circuits is different and varies in a given scope, which induces the time uncertainty of the waveform.
由于制造设备本身存在微小误差，具体门的延时并不相同，而是在一定范围内变化，引起波形变化的时间不确定。
Due to the subtle error among different manufacturing equipment, the gate delay of circuits is different and varies in a given scope, which induces the time uncertainty of the waveform.
由于制造设备本身存在微小误差，具体门的延时并不相同，而是在一定范围内变化，引起波形变化的时间不确定。
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