It is mainly composed of DMA controller (82c37), interrupt controller (82c59), programmable interval timers (82c54), DRAM refresh control, wait state generator and system reset logic.
其内部主要由DMA控制器(82c37)、中断控制器(82c59)、可编程间隔计时器(82c54)，DRAM刷新控制器，等待状态产生器，系统重置电路组成。
The refresh cycles are usually performed by a peripheral called a DRAM controller.
刷新周期一般由一个叫DRAM控制器的外设完成。
While the internal reset signal is being applied to the CPU, the rate of a refresh signal being generated by a DRAM controller for refreshing data in DRAM is increased.
在将内部复位信号加到CPU的同时，提高由DRAM控制器所生成的用于刷新DRAM中数据的刷新信号的速率。
Thee refresh cycles are usually performed by a peripheral called a DRAM controller.
刷新周期一般由一个叫DRAM控制器的外设完成。
Once data has been written in DRAM, charges stored in each capacitor must maintain more than the refresh time so that the information stored in each DRAM cell can be read out correctly.
数据一旦被写进DRAM，每个小电容上电荷的存储时间就必须大于DRAM的刷新脉冲时间，如果由于漏电流致使存储的电荷丢失，就会导致数据读取的误操作。
Once data has been written in DRAM, charges stored in each capacitor must maintain more than the refresh time so that the information stored in each DRAM cell can be read out correctly.
数据一旦被写进DRAM，每个小电容上电荷的存储时间就必须大于DRAM的刷新脉冲时间，如果由于漏电流致使存储的电荷丢失，就会导致数据读取的误操作。
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