一短声记忆体充电 (DRAM refresh) 失败 二短声记忆体同位检查 (Parity check) 错误 三短声记忆体 (Base 64K) 测试失败 四短声系统计时器 (Timer) 失效 五短声处理...
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It is mainly composed of DMA controller (82c37), interrupt controller (82c59), programmable interval timers (82c54), DRAM refresh control, wait state generator and system reset logic.
其内部主要由DMA控制器(82c37)、中断控制器(82c59)、可编程间隔计时器(82c54)，DRAM刷新控制器，等待状态产生器，系统重置电路组成。
The refresh cycles are usually performed by a peripheral called a DRAM controller.
刷新周期一般由一个叫DRAM控制器的外设完成。
While the internal reset signal is being applied to the CPU, the rate of a refresh signal being generated by a DRAM controller for refreshing data in DRAM is increased.
在将内部复位信号加到CPU的同时，提高由DRAM控制器所生成的用于刷新DRAM中数据的刷新信号的速率。
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