A new physical model for on-chip interconnect on high lossy substrate is proposed based on complex image theory and PEEC.
针对高损耗衬底，基于复镜像理论，结合部分元等效电路法，建立了一种新的片上互连线物理模型。
The design and implementation of high speed low power VLSI structure and the analysis and design of high performance on-chip interconnect are two key fields of VLSI design.
高速低功耗VLSI结构的设计实现以及片内高性能互连线的分析设计是VLSI设计的两个关键领域。
The influence of parasitic interconnect capacitance is much in evidence with the progress of the semiconductor techniques and the increase of chip density and calculated speed.
随着半导体工艺的进步，芯片集成度和运算速度的提高，互连寄生效应的影响也日益明显。
And other manufacturing technologies-interconnect between the chip and microstrip, manufacture of microstrip, solderability of available materials and soldering process are discussed.
同时研究了芯片与微带线间距的互连、微带线制作、材料的可焊性及焊接过程等制造技术。
In this embodiment, graphics local memory has a direct interconnect to this integrated chip.
在这个实施例中，图形本地存储器具有到这个集成芯片的直接互连。
In this embodiment, graphics local memory has a direct interconnect to this integrated chip.
在这个实施例中，图形本地存储器具有到这个集成芯片的直接互连。
应用推荐