on-chip interconnect 片内互连
multi chip interconnect 多芯片互连
chip interconnect technology 芯片互连技术
Chip and module interconnect bus 片及模块间互连总线
High Speed Interconnect chip 高速互连芯片
Hybrid Interconnect on Chip 混合片上互连
on-chip global interconnect 片上长线互连
A new physical model for on-chip interconnect on high lossy substrate is proposed based on complex image theory and PEEC.
针对高损耗衬底，基于复镜像理论，结合部分元等效电路法，建立了一种新的片上互连线物理模型。
The design and implementation of high speed low power VLSI structure and the analysis and design of high performance on-chip interconnect are two key fields of VLSI design.
高速低功耗VLSI结构的设计实现以及片内高性能互连线的分析设计是VLSI设计的两个关键领域。
The influence of parasitic interconnect capacitance is much in evidence with the progress of the semiconductor techniques and the increase of chip density and calculated speed.
随着半导体工艺的进步，芯片集成度和运算速度的提高，互连寄生效应的影响也日益明显。
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