Bit synchronous clock recover circuit is the key part of the communication system, it can exactly recover the synchronous signal from input data stream.
位同步时钟信号的提取是通信系统中的关键部分，应用数字锁相环可以准确地从输入码流中提取出位同步信号。
The maximum peak-to-peak value of the timing variations in synchronous data expressed as a percentage of the ideal bit period.
在以理想的位周期的百分数表示的同步数据里，用以表示两个峰值间的最大定时变化值。
The digital realization of monostable circuit and extraction of bit-synchronous signal with digital phase lock loop are also introduced in detail.
对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。
This paper discusses extraction of the bit-synchronous signal with a first-order ADPLL mainly.
本文主要以一阶环为例讨论位同步信号提取。
Compared with conventional circuits, the recovered parallel data is bit-synchronous, and the reference clock is avoided.
与传统并行数据恢复电路相比，该电路不需要本地参考时钟，并且恢复出的并行数据是位同步的。
Traditional Lag-Lead synchronous DPLL shortcomings slow. In order to solve this problem, proposed a method for FPGA-based realization method of fast bit synchronization.
针对传统超前-滞后型数字锁相环实现同步速度较慢的缺点，提出了一种基于步进和量化调整的数字锁相法的快速位同步方法。
The comparing program in VB, how to produce a pseudorandom bit stream, and how to make the compared synchronous data correspondingly is described.
说明硬件测试中伪随机码序列特点和生成原理，并对比较时如何使数据对应做出讨论。
In the fourth chapter of the thesis the principle of evaluating the bit rate error by synchronous and asynchronous histogram were shown.
论文第四章论述了信号幅度柱状图法估算取样信号误码率的原理和方法。
This paper presents a new type of all digital phase-locked loop(ADPLL)used for extracting a bit-synchronous signal to meet the requirements of the fast phase-locked in burst digital communication.
本文根据突发式数字通信快速锁相要求，提出一种位同步信号提取的新的快速全数字锁相环方案。
OTN VCAT static support bit-synchronous mapping mode and asynchronous mapping mode based on scenarios, for optimizing resources and scalability design.
根据应用场景静态支持比特同步映射模式和异步映射模式，实现了资源最优化配置和可扩展性设计。
OTN VCAT static support bit-synchronous mapping mode and asynchronous mapping mode based on scenarios, for optimizing resources and scalability design.
根据应用场景静态支持比特同步映射模式和异步映射模式，实现了资源最优化配置和可扩展性设计。
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