记下钻头系列号和型号。
The bit serial adder system was chosen over a normal gear system because of the number of gears it takes to make the clock's calculations.
该位串行加法器系统是选择了一个由于齿轮数齿轮系统的正常需要，使时钟的计算。
A 48-bit serial number is factory lasered into each DS1991 to provide a guaranteed unique identity which allows for absolute traceability.
每片DS1991内部都有在工厂 光刻的48位序列码，为唯一的身份验证提供了保证，也确保了可绝对跟踪功能；
The driving component includes: a N-bit serial buffer, a K-bit extension buffer, a N-bit video data buffer and N driving current output ports.
该驱动元件包括：一N个位的串序缓冲器，一K个位的延伸缓存器，一N个位的影像资料缓存器，N个驱动电流输出端口。
Using binary notation, 26 movable bit levers inside each bit serial adder convert the swing from the pendulum into a visible notation on the clock.
使用二进制表示法，在每个26位串行加法器动产位的杠杆转换成一个钟摆在摆动的时钟可见符号。
The implementation scheme of digital latch system with 7 bit serial code is discussed and tested. The obtained results show the structure of system designed by this method is simple and practical.
本文对7位串行码数字锁系统这一逻辑命题进行了实施方案的探讨和实验，证明用这种方法设计的系统结构简单实用。
The most obvious issue is that the interface in Listing 6 requires a JNI call for each bit set or retrieved, as well as a JNI call to read a byte from, or write a byte to, the serial port.
最显著的一个问题就是，清单6中的接口在设置或检索每个位，以及从串行端口读取字节或者向串行端口写入字节都需要一个JNI调用。
Serial number: A unique 32-bit non-zero positive number.
序号（Serialnumber）：一个惟一的32 位非零正数。
The multiplier in this paper is Bit-serial mode and the new hardware architecture is regular which reduces the delay of the critical path.
新的乘法器采用比特串行方式，使得硬件结构更加规则，减少了原有乘法器关键路径的延迟。
The first part realizes the collection of the serial data by the AD574A and two CD4051 carrying out the 16-Channal 12-Bit A/D transition.
模块中主要分为两部分，第一部分由AD574A芯片和两个多路开关CD4051实现16路12位A/D转换，完成串行数据的采集；
A new bit-serial modular multiplication based on optimal normal and shifted canonical was presented.
研究中提出了新的基于正规基和正则基的比特串行模乘算法实现方案。
The serial data stream from the DOUT pin has a channel identifier bit and a mode identifier bit, which provide information about the channel converted and the current mode of operation.
DOUT引脚的串行数据流有一个通道识别位和一个模式识别位，可提供所转换通道和当前工作模式的相关信息。
After video information read by FPGA, serial video information is transformed into parallel format by Bit-Plane Separation technology first, and then sent to video cable.
在FPGA读取视频信息后，先用位面分层技术把串行视频信息转换为并行数据再送到视频电缆上。
The new data process path in Baseband is constructed to optimize hardware resource when it is realized by the means of serial bit processing.
给出了新的蓝牙基带的数据处理路径结构，采用串行方式实现可优化硬件资源。
The serial structured decoder can decode one bit per cycle. Because the structure of UVLC(Universal Veriable Length Code) is fixed, "first one detector"is designed to decode UVLC.
变字长解码模块的核心是基于桶形移位器的并行解码结构，使用该结构的解码速度比一次一位的串行结构更快。
The technique used by most electromechanical serial? devices such as teletypewriters, with this technique, each character consists of three parts: a start bit, the data bits and a stop bit.
多数机电串行设备如电传打字机所经常使用的一种传输技术。采用这种技术时，每个字符由一个起始位、干数据位和一个停止位三部分组成。
Baud: The rate at which data is received or transmitted in serial: one baud is one bit per second.
波特：连续接收和传输数据的速率；一波特定义为每秒一个比特。
It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port.
它内置一个低功耗、高速、16位不失码的采样adc、一个内部转换时钟和一个多功能串行接口。
Controller and sensor adopt 8-bit PIC serial single chip processor PIC16F84A and photoelectric interpretation device TLP909 respectively.
控制器和传感器分别采用8位PIC系列单片机pic 16f84 A和光电判读器TLP909。
Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface.
设置与控制的编程利用3位SPI兼容串行接口来完成。
This paper presents the design of extended interface in serial communication with 8n-bit binary number.
本文给出了8n位二进制数串行通讯扩展接口板的设计。
With the serial communication into more applications, so in some applications, the need for communication of message identification bit allocation proposed standardization requirements.
随着串行通讯进入更多应用领域，因此，在一些应用里，需要对通讯功能的报文识别位提出分配标准化的要求。
We introduced the application of a serial of self-made instruments such as electric knife bit, retractor, deep knotter in minicholecystectomy(MC).
介绍自制器械包括电刀头、宽头拉钩、深部打结器在小切口胆囊切除术的应用。
It contains a low power, high speed, 18-bit sampling ADC and a versatile serial interface port.
它内置一个低功耗、高速、18位采样adc和一个多功能串行接口端口。
It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.
它内置一个16位高速采样adc、一个内部转换时钟、一个内部基准电压源(和缓冲)、纠错电路，以及串行和并行系统接口端口。
Thus, tuning can be accomplished via a 2-byte serial transfer to the 16-bit N register.
因此通过16比特N寄存器的2字节串行转换，调谐就可以实现。
The part contains a high-speed 18-bit samplingADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports.
该器件内置一个高速18位采样ADC、一个内部转换时钟、一个内部基准电压缓冲、纠错电路，以及串行和并行系统接口。
The part contains a high-speed 18-bit samplingADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports.
该器件内置一个高速18位采样ADC、一个内部转换时钟、一个内部基准电压缓冲、纠错电路，以及串行和并行系统接口。
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