The implementation scheme of digital latch system with 7 bit serial code is discussed and tested. The obtained results show the structure of system designed by this method is simple and practical.
本文对7位串行码数字锁系统这一逻辑命题进行了实施方案的探讨和实验，证明用这种方法设计的系统结构简单实用。
The multiplier in this paper is Bit-serial mode and the new hardware architecture is regular which reduces the delay of the critical path.
新的乘法器采用比特串行方式，使得硬件结构更加规则，减少了原有乘法器关键路径的延迟。
The multiplier in this paper is Bit-serial mode and the new hardware architecture is regular which reduces the delay of the critical path.
新的乘法器采用比特串行方式，使得硬件结构更加规则，减少了原有乘法器关键路径的延迟。
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