The advantage of dual basis bit parallel multiplier in terms of the scale of hardware is explained.
说明了对偶基比特并行乘法器在硬件规模上的优越性。
The method of designing a parameter configurable and multi-bit parallel BCH decoder is studied in this paper.
本文对可配置参数的多位并行bch译码器的设计方法进行了研究。
This paper present a new method which can accomplish the CRC check with only one 64 - bit parallel CRC check unit.
本文提出了一种只需64位的校验单元即可实现其CRC校验的方法。
Based on these, an algorithm to optimize MDS codes is introduced by analyzing the complexity of bit parallel multipliers.
在此基础上，借助于对比特级并行乘法器的复杂度的分析，给出了一个优化最大距离可分码的算法。
SCSI-1 defined an 8-bit parallel interface with a 5MHz data clock, providing a maximum data transfer rate of 5 megabytes per second (MB/s).
SCSI-1定义了一种具有5MHz数据时钟的8-bit并行接口，能提供最高 5 兆字节每秒（5MB/s）的数据传输速率。
The experimental results prove that this 16 Bit parallel data communication interface attains the performance index and accomplishes the task of c...
通过实际运行证明该16位并行输入输出接口通讯电路达到了设计指标，圆满完成了配合整个控制系统的任务。
The output number delivers to 8 section of LED after 74164 outputs8 bit parallel data, the realization survey data demonstration, realizes visibly count...
输出数经74164输出的8位并行数据送至8段LED，实现测量数据的显示，实现可视的计数功能。
By selecting the bit parallel multiplier based on WDB and the modified BM iterative algorithm that can avoid inversion, the widely used rs decoder is constructed.
采用了一种可以避免求逆运算的修正BM迭代算法，并且利用这样的迭代算法和基于弱对偶基的比特并行乘法器构成了广泛应用的RS码的译码器。
Assemble language was used to write second boot loader, and 16-bit parallel asynchronous memory Loading mode was adopted to achieve automatic run after energization.
应用汇编语言编写了二次引导程序，采用16位并行异步存储器加载方式，实现计量单元上电自动运行。
The presentation of the finite field elements in WDB is studied. And based on the computing method for the optimum WDB, the design for the bit parallel multiplier of finite field is presented.
研究了有限域元素在弱对偶基（WDB）下的表示，基于弱对偶基下的最优弱对偶基的计算方法，给出了有限域比特并行乘法器的设计；
Bruce Shapiro got me to design and build the UBW (USB Bit Whacker) project to solve his problem of disappearing parallel ports on computers.
BruceShapiro找我来搞了个UBW项目(使用usb接口的驱动板)，以解决他电脑上没有并行接口的问题。
Every operation works on multiple data elements in parallel, stored in 128-bit registers.
每个操作都是并行地针对多个数据元素进行，这些数据分别存储在一些128位的寄存器中。
However, in line with the modest capabilities of the iMic, our target for this series is to work with two parallel (stereo) 44.1khz 16-bit data streams, implying an audio bandwidth of 22.05khz.
然而，为了让iMic具有适度的性能，我们在本系列文章中的目标是处理两个并行的(立体声)44.1kHz的16位数据流，这就意味着要实现22.05 kHz的音频带宽。
We found a house in the road parallel to ours but it was a bit dark and damp.
我们发现了街道上有一处与我们平行的住宅，但它光线不好且潮湿。
In this paper we briefly introduce some basic concepts of quantum computing which include quantum entanglement, quantum bit, quantum register, quantum parallel computing and quantum error correction.
本文简要地介绍量子计算的一些基本概念：量子纠缠、量子位、量子寄存器、量子并行计算和量子纠错。
A new parallel algorithm is also proposed for the head error correct (HEC) module, it can not only detect multi bit error but also correct one bit error.
提出了一种新的信头误码校正(HEC)并行算法，能检测到多个比特错误，并能纠正单比特错误。
After video information read by FPGA, serial video information is transformed into parallel format by Bit-Plane Separation technology first, and then sent to video cable.
在FPGA读取视频信息后，先用位面分层技术把串行视频信息转换为并行数据再送到视频电缆上。
Bit planes are coded by context format (CF) modules in parallel.
采用与位平面数目相同的上下文形成模块实现位平面并行处理。
According to the research on the existing VLSI architecture of the bit-plane coding, a new VLSI architecture is proposed in which stripe-column and coding are both implemented in parallel.
研究了现有的位平面编码VLSI结构，设计了一种条带列与编码通道全并行的VLSI结构，解决了内部存储资源占用率高的问题。
Compared with conventional circuits, the recovered parallel data is bit-synchronous, and the reference clock is avoided.
与传统并行数据恢复电路相比，该电路不需要本地参考时钟，并且恢复出的并行数据是位同步的。
For fast encoding, the bit-plane and pass dual-parallel approach is presented in this paper, which reduces the encoding time significantly.
为实现快速编码，该文提出一种位平面、过程双重并行编码方法，可以大幅度提高编码速度。
When the Security Bit is activated all parallel PROGRAMMING commands except for Chip-Erase are ignored (thus the DEVICE cannot be read).
当保密位被激活后，除芯片擦除外的所有并行编程命令都被忽略(这样就不能对器件执行读操作)。
The compression ratio of algorithm is more than 1.9. The compression algorithm based on bit plane transform can be realized by parallel computing model.
压缩比达到了1.9以上，与其它超光谱图像压缩算法相当。位平面变换算法具有很好的并行性。
This parallel processing method is fit for other bit-wide CRC, and provides reliability for high-speed data transferring as well.
同时这种并行处理方法也适合于其它位宽的CRC电路，为高速数据的可靠传输提供了可靠保障。
The MQ coder is adopted in JPEG2000. In EBCOT algorithm, the tiles, code-block, bit-plane all can be implemented using parallel structure.
同时，在JPEG 2000中基于子带、码块和比特平面的编码都可以并行实现。 因此，MQ编码器的效率就成了JPEG 2000硬件高速实现需要解决的关键问题。
It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.
它内置一个16位高速采样adc、一个内部转换时钟、一个内部基准电压源(和缓冲)、纠错电路，以及串行和并行系统接口端口。
In this paper, we present a bit plane-parallel architecture for zero tree coding which is suitable for VLSI implementation.
提出了比特平面并行处理的零树编码结构。
After the detailed analysis of EBCOT algorithm and pass-parallel coding technique, a dual context window bit-parallel coding method and its architecture for hardware implementation are proposed.
通过研究EBCOT编码原理和通道并行算法的编码过程，提出了双上下文窗口位并行的EBCOT系数位建模方法，详细说明了使用该算法的系数位建模系统的硬件结构。
After the detailed analysis of EBCOT algorithm and pass-parallel coding technique, a dual context window bit-parallel coding method and its architecture for hardware implementation are proposed.
通过研究EBCOT编码原理和通道并行算法的编码过程，提出了双上下文窗口位并行的EBCOT系数位建模方法，详细说明了使用该算法的系数位建模系统的硬件结构。
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