The advantage of dual basis bit parallel multiplier in terms of the scale of hardware is explained.
说明了对偶基比特并行乘法器在硬件规模上的优越性。
The method of designing a parameter configurable and multi-bit parallel BCH decoder is studied in this paper.
本文对可配置参数的多位并行bch译码器的设计方法进行了研究。
This paper present a new method which can accomplish the CRC check with only one 64 - bit parallel CRC check unit.
本文提出了一种只需64位的校验单元即可实现其CRC校验的方法。
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