Fault simulation is an important part of ATPG.
故障模拟是数字电路测试的重要组成部分。
Based on existing parallel techniques, this paper proposes a dynamic hierarchical framework for parallel ATPG and gives an implementation scheme.
本文在总结已有并行技术的基础上，提出了并行测试生成系统的一种动态层次框架，并给出了一种实现方案。
This dissertation focuses on automatic test generation (ATPG) algorithms for very large-scale integrated circuits at register-transfer-level (RTL).
本文主要是对大规模、超大规模集成电路寄存器传输级（RTL）的自动测试产生算法进行研究。
The BSDL language that describes boundary scan components is thoroughly studied, and then applied to boundary scan ATPG tools and fault diagnosis software.
在对描述器件边界扫描特性的BSDL语言进行了深入研究之后，将其应用于边界扫描自动测试图形生成atpg与故障诊断软件中。
The analyses reveal that, compared with traditional tightly coupled mode parallel ATPG algorithms, loosely coupled mode parallel ATPG algorithms can reduce time and memory overhead in theory.
分析表明，和传统的紧耦合模式的并行atpg算法相比，松耦合模式的并行atpg算法能够减少时间和存储开销。
The analyses reveal that, compared with traditional tightly coupled mode parallel ATPG algorithms, loosely coupled mode parallel ATPG algorithms can reduce time and memory overhead in theory.
分析表明，和传统的紧耦合模式的并行atpg算法相比，松耦合模式的并行atpg算法能够减少时间和存储开销。
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