There are many ways to do asynchronous FIFO design, including many wrong ways.
设计异步FIFO 的方法有很多，当然有很多的方法是不对的。
Asynchronous FIFO is a general way to communicate between different clock domains.
异步fifo是一种不同时钟域之间传递数据的常用方法。
Metastability and how to generate empty and full flag correctly is key in the design of asynchronous FIFO.
避免亚稳态问题及空满控制信号的产生是异步fifo设计的两个关键。
The design of asynchronous FIFO meets with two troubles, metastability and how to generate empty and full flag correctly.
避免亚稳态问题及空满控制信号的产生是异步fifo设计的两个难题。
In this article, we introduce the ping pong operation into the asynchronous FIFO design and provide a FIFO design scheme in FPGA.
根据异步fifo的设计方法，引入乒乓操作的设计技巧，给出了一种用FPGA实现异步fifo的设计方案。
We have designed an in-chip high speed asynchronous FIFO to reduce the sample rate, the simulation results shows it can be used to reduce system resource cost and it has very low access time.
我们设计实现了片内高速异步fifo以降低采样率，仿真结果表明资源使用合理且访问时间很小。
A new FIFO-based asynchronous wrapper was proposed, which implemented using only standard cell and optimized in a standard digital ASIC flow.
本文采用通用的数字ASIC设计流程，在仅使用已有标准单元的情况下，提出了一种新的基于FIFO的异步包装。
Asynchronous First In First Out (FIFO) is adopted to synchronize data transfer between APB bus and I2C bus.
设计中采用了异步先进先出来同步apb总线和I2C总线之间的数据交换。
Asynchronous First In First Out (FIFO) is adopted to synchronize data transfer between APB bus and I2C bus.
设计中采用了异步先进先出来同步apb总线和I2C总线之间的数据交换。
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