本文给出一种任意多位的保留进位阵列乘法器的自动设计方法。
This paper presents an automatic design method for a carry save array multiplier with arbitrary number of bits.
直接补码阵列乘法器的工作原理是《计算机组成原理》课程的难点。
The direct 2's complement array multiplier principle of work is "Computer Organization Principle" the curriculum difficulty.
传统的乘法器的设计，在最终的乘积项求和时，常采用阵列相加或叠代相加的方法，不适用中小规模的微处理器的设计。
In summing of the last product in the traditional multiplier design, the array or iteration summing method is used, which is not suitable to the design of small or middle scale integration circuit.
根据平行并行乘法器，设计了适用于模乘运算的一维阵列组合乘法器。
The one-array combinative multiplication was designed on the basis of the parallel multiplication.
通过给出一个用通用阵列逻辑芯片GAL开发二进制比例乘法器的事例，详细介绍了用GAL芯片开发高集成度逻辑电路的方法。
By giving an example which USES GAL to develop a binary ratio multiplier, the author explains in detail the method of using GAL chip to develop a high-density integrated circuit.
设计完成的乘法器只产生9个部分积，有效降低了部分积压缩阵列的规模与延时。
The designed multiplier has only 9 partial products, which effectively reduces the size and delay of compression array.
设计完成的乘法器只产生9个部分积，有效降低了部分积压缩阵列的规模与延时。
The designed multiplier has only 9 partial products, which effectively reduces the size and delay of compression array.
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