当今信息具有存储量大、传输速度快、可靠性高等现实需求，芯片互连技术在其中发挥着重要作用。
Today's information have the performance of high capacity, fast transmission and high reliability, chip interconnection plays a critical role in it.
介绍了MCM-C的CAD设计方法，以及MCM-C基板的制作与金属化、芯片的测试和老化、芯片互连等工艺。
This paper describes the CAD method for MCM-C, the fabrication and metallization processes of MCM-C substrates, and the technologies for die test, burn-in and interconnection.
在一个集成电路中，多个芯片、共享内存以及互连形成了一个紧密集成的多处理核心(参见图4)。
On a single integrated circuit, multiple chips, Shared memory, and an interconnect form a tightly integrated core for multiprocessing (see Figure 4).
SRIO处理器是一个互连技术，并用一个背板使电路板上的芯片相互连接。
A Rapid IO Processor is an inter-connect technology that connects chips on a circuit board and circuit boards to each other using a backplane.
随着半导体工艺的进步，芯片集成度和运算速度的提高，互连寄生效应的影响也日益明显。
The influence of parasitic interconnect capacitance is much in evidence with the progress of the semiconductor techniques and the increase of chip density and calculated speed.
同时研究了芯片与微带线间距的互连、微带线制作、材料的可焊性及焊接过程等制造技术。
And other manufacturing technologies-interconnect between the chip and microstrip, manufacture of microstrip, solderability of available materials and soldering process are discussed.
应用需求的增长和系统芯片集成度的不断提高，对系统芯片片上互连结构提出了更高的要求。
Higher performance of the on-chip interconnection is needed because of the improvement of the system-on-chip integration and application requirements.
随着IC的高速化、高集成化、高密度化和高性能化，芯片内互连线之间的串扰已经成为影响芯片性能的重要因素之一。
With the IC's higher speed, higher integration, higher density and higher performance, crosstalk has become one of the most important factors which can influence the IC's performance.
将实现3d互连的方法分为引线键合、倒装芯片、硅通孔、薄膜导线等，并对它们的优缺点进行了分析。
The methods of 3d interconnection can be classified into the wire bonding, flip chip, through silicon via (TSV) and film wire technology, whose advantages and disadvantages are analyzed.
以自行研制的PCI-A429芯片为例，讨论了内核设计以及系统集成中内核互连的问题。
The approach of the IP-Core design and IP-Core interconnection in the integrated system are discussed with the example of the Chip PCI-A429 developed by CARERI in this paper.
在这个实施例中，图形本地存储器具有到这个集成芯片的直接互连。
In this embodiment, graphics local memory has a direct interconnect to this integrated chip.
本文首次利用时域有限差分(FDTD)法分析了高速集成电路芯片内半导体基片上的有耗互连传输线的电特性。
A full wave analysis of lossy interconnection lines on doped semiconductor substrates in high speed integrated circuits is carried out by means of a finite difference time domain (FDTD) approach.
分析结果表明，该方法很适合高速集成电路芯片内互连线的计算机辅助分析。
The results show that this method is very fit for the computer aided analysis of on chip interconnects for the high speed VLSI.
本文提出了一种用于求解高速VLSI和多芯片组件(MCM)中有耗互连线瞬态响应的稳定递归算法。
A stable recursive algorithm is presented for the transient simulation of interconnect systems in the high-speed VLSI and multichip modules (MCMs).
垂直通孔互连是微波多芯片组件封装工艺和理论分析的基础，开展垂直通孔互连的研究有着现实的意义。
Because vertical via interconnect is the base of theoretical analysis and package technics of MMCM, further study on vertical via interconnect is very vital and instructive to reality.
本论文研究了MCM中芯片安装互连、芯片倒装焊接及其关键支撑技术等内容。
This paper talks about the major supporting technologies for MCM package: the Interlinkage of Chips, Flip Chip Bonding, Flip Bonding.
本文使用导体截面矩量法提取芯片内互连线电阻和电感频变分布参数。
Conductor cross-section method of moment is applied in extracting resistance and inductance frequency-dependent distributed parameter of IC interconnects.
在一个实施例中，图形本地存储控制器也集成到芯片组408上，以便提供通过互连418对图形本地存储器416的访问。
In one embodiment, graphics local memory controller is also integrated on chipset 408 to provide access to graphics local memory 416 through interconnect 418.
耦合到中央处理器100以及芯片组102的互连104用于这两个代理之间的通信。
Interconnect 104, coupled to both central processor 100 and chipset 102, is used for communication between these two agents.
通过建立互连资源估计的随机模型，提出了可重构计算芯片中各种互连资源数目的估计方法。
By establishing stochastic model for connecting resource estimation, an approach to estimate the number of connecting resource for rc is presented.
互连410提供中央处理器400与芯片组408之间的通信链路。
Interconnect 410 provides a communication link between central processor 400 and chipset 408.
在一个实施例中，集成到芯片组102上的系统存储控制器106对中央处理器100提供通过互连110对系统存储器子系统108的访问。
System memory controller 106, integrated on chipset 102 in one embodiment, provides central processor 100 access to the system memory subsystem 108 through interconnect 110.
中央处理器302和图形处理器304通过互连308与芯片组306进行通信。
Central processor 302 and graphics processor 304 communicate with chipset 306 through interconnect 308.
这种新型的硅基发光管结构在下一代集成电路中作为芯片之间或芯片内部的光互连具有非常广阔的应用前景。
The new type silicon-based luminous tube structure has a widely application prospect as light connection between chips or chips inner in next generation integrated circuit.
分别采用三种不同的技术对多芯片组件互连延迟进行建模，并给出了相应的解。
Interconnection delay in MCM 's is modeled by using three different techniques, and the associated formulas are also derived.
COF是一种高性能、多芯片封装工艺技术，在此封装中把芯片包入模塑塑料基板中，通过在元器件上形成的薄膜结构构成互连。
COF is a high performance, multichip packaging technology in which dies are encased in a molded plastic substrate and interconnects are made via a thin-film structure formed over the components.
第四章对光互连理论进行研究，讨论基于微谐振器的芯片光互连交换单元的设计并评估其性能。
In chapter 4, we study the theory of optical interconnection and discuss the design of switching unit of optical Network-on-Chip based on micro-resonator.
第四章对光互连理论进行研究，讨论基于微谐振器的芯片光互连交换单元的设计并评估其性能。
In chapter 4, we study the theory of optical interconnection and discuss the design of switching unit of optical Network-on-Chip based on micro-resonator.
应用推荐