为了为这个实用程序设计尽可能快的架构，在对缓冲区操纵者编写代码时，已经使它不必将数据发给特定的控制器。
To architect this utility to run as a fast as possible, the buffer manipulator has been coded such that it doesn't have to give data to a specific device controller.
当DRNN预测下一时刻缓冲区中的信元数超过阈值时，控制器产生一个反馈控制信号减小信源进入网络的信元速率以避免拥塞发生。
When DRNN predicts that the number of cells in buffer exceeds the threshold limit in the next time cycle, a control signal is generated by the controller to throttle arrival cell rate.
针对单输入单输出和多输入多输出网络控制系统中存在的时延抖动和时延偏移问题，提出了在控制器和执行器前设置缓冲区的方法。
For the problems of delay jitter and delay skew consisting in SISO and MIMO networked control systems, the method of setting buffers before controller and action is bring forward.
该策略基于缓冲区单次拷贝技术，克服了有些嵌入式系统存储控制器低效的存储块拷贝。
Based on the single buffer copy technology, the strategy overcomes the inefficiency of storage block copy in some embedded system's memory control unit.
EPCTL 完成设备控制器内集成的3对端点缓冲区的读写控制。
EPCTL controls the 3 pairs of endpoints of the device controller's writing and reading operations.
每一个CAN控制器提供给每个CAN通道一个双接受缓冲区来存储接受的信息直到他们被CPU处理掉。
Each CAN controller provides a double Receive Buffer (RBX) per CAN channel to store incoming messages until they are processed by the CPU.
该控制器从外部重写装置接收数据块并将其存储在第一个缓冲区。
The controller receives a data block from an external rewriting device to store it in the first buffer.
FPGA实现MV B控制器功能，分为曼彻斯特编码器、解码器、缓冲区、中央控制单元、内部存储器和单片机接口等几部分。
The FPGA is designed as a MVB controller which consists of Manchester encoder, Manchester decoder, buffer, center control unit, internal memory, MCU interface and so on.
FPGA实现MV B控制器功能，分为曼彻斯特编码器、解码器、缓冲区、中央控制单元、内部存储器和单片机接口等几部分。
The FPGA is designed as a MVB controller which consists of Manchester encoder, Manchester decoder, buffer, center control unit, internal memory, MCU interface and so on.
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