使用V形槽工艺，用溅射铝的方法代替扩硼工艺制备静电感应晶体管的栅极区，简化了工艺流程，使器件在调试过程中具有很大灵活性。
The gate region was fabricated by V-groove and Al sputtering, which can simplify the process, and make devices flexible in the adjustment process.
特定来说，在非易失性存储器装置经历许多编程循环时，电荷变为俘获在浮动栅极与沟道区之间的绝缘体或电介质中。
In particular, as a non-volatile memory device undergoes many programming cycles, charge becomes trapped in the insulator or dielectric between the floating gate and the channel region.
各种MOSFET测试都要求进行弱电流的测量。这些测试包括栅极漏电、泄漏电流与温度的关系、衬底对漏极的漏电和亚阈区电流等。
Various MOSFET tests require making low current measurements. Some of these tests include gate leakage, leakage current vs. temperature, substrate to-drain leakage, and sub-threshold current.
在半导体中的源极区和漏极区可以限定晶体管栅极长度。
Source and drain regions in the semiconductor may define a transistor gate length.
浮动栅极定位于源极区与漏极区之间。
The floating gate is positioned between the source and drain regions.
此外，该多阶式栅极结构另包含多个掺杂浓度不同的掺杂区，设置在该多层阶梯结构下方的半导体基板中。
In addition, multilayer staircase type grid structure includes multiple doping sections with different doping densities setup in semiconductor base plate in low part of MSS.
所述半导体器件还包括沟槽栅极(32)，其通过绝缘层(33)面对部分所述中间区。
The semiconductor device further has a trench gate (32) facing a portion of the intermediate region via an insulating layer (33).
源区和漏区形成在鳍部内栅极的相对侧处。
A source region and a drain region are formed in the fin at the opposite sides of the gate electrode.
源区和漏区形成在鳍部内栅极的相对侧处。
A source region and a drain region are formed in the fin at the opposite sides of the gate electrode.
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