1mhz等于每秒一百万个指令周期。
此时间间隔的默认值为单个指令周期(10毫秒)。
The default value for this interval is a single clock tick (10 milliseconds).
指令周期是微处理器通过对指令进行处理的过程。
The instruction cycle is the procedure a microprocessor goes through to process an instruction.
如何添加c在一个单一的指令周期100的整数数组？
How to add array of 100 integer elements in a single instruction cycle in c?
但是由于指令周期考虑不全和硬件自身的原因易引起定时误差。
Because instruction period is not completely considered and the hard ware is not perfect, it is easy to cause error.
在单指令流单数据流结构中，有单一的指令周期，在执行前，单个处理机按序取操作数。
In an SISD architecture there is a single instruction cycle; operands are fetched serially into a single processing unit before execution.
在那些日子里，使用电脑意味着编写代码保存一个字节在这里，一个指令周期后又再取出来放到那里。
In those days, working with computers meant writing code to save a byte here and an instruction cycle there.
为了能实现X86指令集全部移位类指令，采用了指令预处理的技术，节省了指令周期，提高了CPU的效率。
In order to conpatible the 8X86shifter instruction , we use the instruction pre-handle technology. In result, it save the instructionhandling cycle and improve the CPU efficiency.
它的第一个设计非常简单，所有指令都在一个时钟周期内完成。
Its first design was very simple and all instructions were completed in one clock cycle.
cpi值越高，则运行指令所需的周期就越多，这意味着程序的运行性能未达到最优。
A higher CPI value indicates that more cycles were necessary to run the instruction, implying suboptimal execution of the program.
从消除信号阻塞到进程执行下一个指令之间，必然会有时钟周期间隙，任何在此时间窗口发生的信号都会丢掉。
There has to be some gap of clock cycles between the unblocking of signals and the next instruction carried by the process, and any occurrence of a signal in this window of time is lost.
您只需要记住提示限制和一个事实：提示指令确实需要占用程序的一个周期。
Just keep in mind the hint restrictions as well as the fact that hint instructions do take up a cycle of your program.
POWER 6处理器有两个能够在每个处理器周期发出多条指令的硬件指令线程，从而改善了性能。
The POWER6 chip has two hardware instruction threads that are both capable of issuing multiple instructions per cycle, which causes a boost in performance.
发出所有指令后，此请求周期即达到了其最后的状态，表明请求处理完毕，如图2所示(要看放大的图片，请单击此处)。
After sending all instructions, the request cycle reaches its final state, which denotes the end of request processing, as shown in Figure 2 (to see a larger image, click here).
POWER 5芯片有两个硬件指令线程，在每个周期都能够执行多个指令，这可以提高性能。
The POWER5 chip has two hardware instruction threads that are both capable of issuing multiple instructions per cycle, which causes a boost in performance.
请求周期会经历若干状态并会根据当前状态向请求周期处理器发出不同的指令。
The request cycle goes through several states and, depending on the current state, sends different instructions to the request cycle processor.
POWER 5微处理器使此吞吐量增加了一倍，每个时钟周期收集两组指令(每组最多有五个)，并在每个时钟周期内完成两组指令。
The POWER5 microprocessor doubles that throughput by collecting two groups of up to five instructions per clock cycle and completing two groups per clock cycle.
在这个程序中，完成指令1需要花费4个时钟周期。
In this program, it takes four clock cycles for instruction 1 to finish.
不过对于现在来说，我们将简单地展示如何通过调整selb和stqd指令的顺序来节省两个时钟周期。
However, for now, I will simply show how to save two clock cycles by adjusting the order of the selb and STQD instructions. Here is the new order.
SPU本身使用向量操作，每个时钟周期可以执行多达8条浮点指令。
An SPU USES vector operations itself and can thereby execute up to eight floating point instructions per clock cycle.
POWER 4微处理器每个时钟周期收集一组指令(最多有5个)，并在每个时钟周期内完成一组指令。
The POWER4 microprocessor collects a group of up to five instructions per clock cycle and can complete one group of instructions per clock cycle.
这需要修改oprofile的内核代码来周期性地对SPU指令指针进行采样。
This requires changes to the OProfile kernel code to sample the SPU instruction Pointers regularly.
要想让分支提示变得非常有效(这样分支就根本不会暂停了)，就必须设置至少4个指令取出组和分支指令之前的11个周期。
For a branch hint to be most effective (so that the branch does not stall at all), it must be set at least four instruction fetch-groups plus 11 cycles before the branch instruction.
请求周期处理器负责处理请求周期内的指令。
The request cycle processor is responsible for handling instructions during the request cycle. It's used by RequestCycle, which calls its methods in the predefined order.
如果这些条件不都满足，或者第二条指令在执行之前需要等待依赖项，那么它们可以在单独的周期中执行。
If these conditions are not all met, or if the second instruction needs to wait for dependencies before issuing, then they are issued in separate cycles.
延时——一条指令用来产生最终值所使用的时钟周期数。
Latency — The number of clock cycles an instruction USES to produce a final value.
除了处理器时钟速度外，另一个重要的处理器性能度量是每条指令的时钟周期(CPI)。
In addition to processor clock speed, another important processor performance metric is clock cycles per instruction (CPI).
流水线是 CPU所使用的一个众所周知的概念，它用于减少取指令-译码-执行 周期中出现的延迟。
Pipelining is a well-known concept employed by CPUs for reducing the latency involved in the fetch-decode-execute cycle.
CPI表示一个指令平均占用多少个周期。
CPI means how many cycles an instruction takes to complete in average.
我们接到了神圣的指令以确保你们的安全完成你们的周期，那些你们之中所有已经选择参与扬升的人都能完成。
We have divine orders to ensure you safely reach the end of this cycle, and that all of you who have elected to ascend are able to do so.
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