改进的输入缓冲方案是在AT M交换单元的输入队列和仲裁逻辑之间加入一个准随机存储器。
The improved model of input buffer presented is to insert a quasi random memory between input queue and arbitration logic at ATM switching unit.
在数据加载操作过程中，可以按与可编程核心逻辑电源电压相等的电源电压对存储器单元供电。
During data loading operations, the memory elements may be powered with a power supply voltage equal to the programmable core logic power supply voltage.
在正常操作过程中，可以按比可编程核心逻辑电源电压高的电源电压对存储器单元供电。
During normal operation the memory elements may be powered with a power supply voltage that is larger than the programmable core logic power supply voltage.
本发明提供了电源电平升高的可编程逻辑器件存储器单元。
Programmable logic device memory elements with elevated power supply levels are provided.
向存储器单元中加载可编程逻辑器件配置数据，来对可编程核心 逻辑进行配置以执行定制逻辑功能。
Programmable logic device configuration data is loaded into the memory elements to configure the programmable core logic to perform a custom logic function.
向存储器单元中加载可编程逻辑器件配置数据，来对可编程核心 逻辑进行配置以执行定制逻辑功能。
Programmable logic device configuration data is loaded into the memory elements to configure the programmable core logic to perform a custom logic function.
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