改进的输入缓冲方案是在AT M交换单元的输入队列和仲裁逻辑之间加入一个准随机存储器。

The improved model of input buffer presented is to insert a quasi random memory between input queue and arbitration logic at ATM switching unit.

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在数据加载操作过程中，可以按与可编程核心逻辑电源电压相等的电源电压对存储器单元供电。

During data loading operations, the memory elements may be powered with a power supply voltage equal to the programmable core logic power supply voltage.

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在正常操作过程中，可以按比可编程核心逻辑电源电压高的电源电压对存储器单元供电。

During normal operation the memory elements may be powered with a power supply voltage that is larger than the programmable core logic power supply voltage.

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