控制电路在预定的存储器周期的开始时刻读出存储器阵列中的数据。
The control circuitry senses data within the memory array at a beginning of a predetermined memory cycle.
缓冲存储器周期的一部分，在这期间，逻辑与算术运算器必须中止操作或不能与存储器传输信息。
A portion of the buffer cycle in which the logic or arithmetic unit must cease operation or neither will be able to communicate with the memory unit.
从主存储器读数据需要较多的CPU周期。
Reading the data from the main memory requires more CPU cycles.
深存储器意味即在捕获长的时间周期时仍能保持高采样率。
Deep memory means that the sample rate stays high even when capturing long time periods.
该系统能发挥两种微机的优势，利用总线周期窃用和分散型共享存储器技术，实现紧耦合方式的高速通信。
The system takes advantage of both, computers and can realize high rate communication in tight coupling style, by using bus period stealing and distributional memory sharing.
在用于对读取周期中读取位线上的剩余电荷放电的半导体存储器装置中，位线在除读取操作期间以外的全部时间均处于复位状态。
In a semiconductor memory device operative to discharge residual charge in a read bit line in a read cycle, the bit line is in the reset state at all times except during read operation.
移动设备内的存储器卡操作与非接收周期同步。
Memory card operations within the mobile device are synchronized to the non-receiving periods.
移动设备内的存储器卡操作与非接收周期同步。
Memory card operations within the mobile device are synchronized to the non-receiving periods.
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