控制电路在预定的存储器周期的开始时刻读出存储器阵列中的数据。
The control circuitry senses data within the memory array at a beginning of a predetermined memory cycle.
缓冲存储器周期的一部分，在这期间，逻辑与算术运算器必须中止操作或不能与存储器传输信息。
A portion of the buffer cycle in which the logic or arithmetic unit must cease operation or neither will be able to communicate with the memory unit.
从主存储器读数据需要较多的CPU周期。
Reading the data from the main memory requires more CPU cycles.
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