设计了一个基于FPGA的高速、高性能的高斯随机数发生器。
A highspeed gaussian random number generator implemented with FPGA is presented in this paper.
为设计一个用于信道仿真和编码器性能测试的高速高斯随机数发生器，研究了适于硬件实现的高速通用的连续随机变量和随机序列产生法。
To design a gaussian random number generator used for channel simulation and coder performance test, high-speed universal random number and correlated stochastic series generators are studied.
依据中心极限定理，用均匀分布随机数求和的方法得到趋于高斯分布的白噪声。
White noise tending to Gaussian distribution is implemented by summing uniformly distributed random numbers according to the central limit theorem.
应用推荐