设计了一个基于FPGA的高速、高性能的高斯随机数发生器。
A highspeed gaussian random number generator implemented with FPGA is presented in this paper.
为设计一个用于信道仿真和编码器性能测试的高速高斯随机数发生器，研究了适于硬件实现的高速通用的连续随机变量和随机序列产生法。
To design a gaussian random number generator used for channel simulation and coder performance test, high-speed universal random number and correlated stochastic series generators are studied.
依据中心极限定理，用均匀分布随机数求和的方法得到趋于高斯分布的白噪声。
White noise tending to Gaussian distribution is implemented by summing uniformly distributed random numbers according to the central limit theorem.
本文提出了一种生成广义高斯分布(GGD)随机数的通用算法。
In this paper, a new algorithm is proposed to generate generalized Gaussian distribution (GGD).
以伪均匀随机数为基础，根据大数中心极限定理，产生高斯分布随机数。
Based on pseudo random uniformity number and the central limit theory of great numeral, random Numbers of Gaussian distribution are produced.
在用蒙特卡罗法进行仿真研究(例如进行测量不确定度评定)时，常常需要发生多个非高斯型互相关的随机数。
In Monte Carlo simulation such as the measurement uncertainty evaluation, it is often necessary to generate correlated multi-non-Gaussian random observations.
在用蒙特卡罗法进行仿真研究(例如进行测量不确定度评定)时，常常需要发生多个非高斯型互相关的随机数。
In Monte Carlo simulation such as the measurement uncertainty evaluation, it is often necessary to generate correlated multi-non-Gaussian random observations.
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