介绍了一种应用直接数字频率综合器（DDS）技术，基于可编程逻辑器件（CPLD）和单片机设计的低频信号源。

According to the technology of direct digital synthesis(DDS), a kind of low frequence signal source was introduced based on the Complex Programmed Logical Device(CPLD)and Single Chip Micyoco(SCM).

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该频率综合器采用模拟调谐和数字调谐相结合的技术来提高相位噪声性能。

A combined tuning technique of digital tuning and analog tuning is used to improve the phase noise of frequency synthesizer by decreasing the gain of VCO.

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PLL混合频率合成技术能综合两者的优点，已成为现今频率合成领域的重要研究方向。

DDS hybrid PLL can take good advantage of both their merit, have become an important area of frequency synthesis.

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