介绍了一种应用直接数字频率综合器（DDS）技术，基于可编程逻辑器件（CPLD）和单片机设计的低频信号源。
According to the technology of direct digital synthesis(DDS), a kind of low frequence signal source was introduced based on the Complex Programmed Logical Device(CPLD)and Single Chip Micyoco(SCM).
该频率综合器采用模拟调谐和数字调谐相结合的技术来提高相位噪声性能。
A combined tuning technique of digital tuning and analog tuning is used to improve the phase noise of frequency synthesizer by decreasing the gain of VCO.
PLL混合频率合成技术能综合两者的优点，已成为现今频率合成领域的重要研究方向。
DDS hybrid PLL can take good advantage of both their merit, have become an important area of frequency synthesis.
该方法对综合研究爆破振动危害机理和爆破地震效应，特别是为构建爆破振动速度频率相关安全准则提供了一种有效的分析技术。
This method is effective for studying the mechanism of blast vibration damage and blast seismic effect in its entirety, specially, for constituting velocity-frequency criteria.
现代频率合成一般综合运用这三种频率合成技术，又称混合频率合成。
The said three techniques are comprehensively applied in the modern frequency synthesis technique, which are also called "Admixture-Frequency synthesis technique".
给出了采用AD985 4芯片构成的低相噪频率综合源的硬件组成以及系统实测的相位噪声、杂散技术指标。
The hardware constitution of a low phase noise frequency synthesizer using AD9854 and the measured performances of system phase noise and spurious spectrum are presented.
本发明公开了一种双环路频率综合器及其粗调环路的调谐方法，属于无线收发机中的 频率综合器技术领域。
The invention discloses a dual-loop frequency synthesizer and a tuning method of rough adjustment loop thereof, belonging to the field of frequency synthesizer in wireless transceiver.
本发明公开了一种双环路频率综合器及其粗调环路的调谐方法，属于无线收发机中的 频率综合器技术领域。
The invention discloses a dual-loop frequency synthesizer and a tuning method of rough adjustment loop thereof, belonging to the field of frequency synthesizer in wireless transceiver.
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