设计时主要考虑两个因素—— 导通电阻和时钟馈通（ clock feedthrough）。设计时，应该尽可能地减小导通电阻和开关 引入的时钟馈通。
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时钟馈通效应 Clock Feedthrough ; clock feed-through effect
This design uses the difference technique and bottom sampling technique to overcome the charge injection effect and the clock feed-through effect.
为了提高A/D转换的精度,本设计采用全差分和下极板采样技术克服电荷注入效应和时钟馈通效应的影响。
参考来源 - 基于低电压高精度12This paper analysis the theory of the comparator and the method of how to decrease the channel charge injection and clock feedthrough,the method can effectively improved the performance of switch capacitor.
文中详细介绍了开关电容比较器的基本工作原理,分析了电路误差的产生机理,在此基础上提出了为减小失调和误差、进一步改善电路性能而采取的抑制开关电容比较器电荷注入和时钟馈通效应提高精度的具体措施。
参考来源 - 一种ADC中采用的开关电容比较器的设计·2,447,543篇论文数据，部分数据来源于NoteExpress
该技术通过消除采样开关有限导通电阻的影响，补偿了采样带宽，并避免了时钟馈通和电荷注入的加剧。
The CEC technique compensates the sampling bandwidth by eliminating the impact from finite on-resistance of the sampling switch, and avoids increasing clock feedthrough and charge injection.
本文分析了直流失调电压以及时钟馈通现象产生的原因，并且结合具体的应用条件提出有针对性的解决方案。
The reasons of DC offset and clock feed-through are analyzed, and pertaining solutions are brought out according to given application conditions.
采样保持电路设计采用了电容下极板采样技术，不仅有效地避免了电荷注入效应引起的采样信号失真，而且消除了时钟馈通效应的不良影响。
The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed-through.
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