该技术通过消除采样开关有限导通电阻的影响，补偿了采样带宽，并避免了时钟馈通和电荷注入的加剧。
The CEC technique compensates the sampling bandwidth by eliminating the impact from finite on-resistance of the sampling switch, and avoids increasing clock feedthrough and charge injection.
本文分析了直流失调电压以及时钟馈通现象产生的原因，并且结合具体的应用条件提出有针对性的解决方案。
The reasons of DC offset and clock feed-through are analyzed, and pertaining solutions are brought out according to given application conditions.
采样保持电路设计采用了电容下极板采样技术，不仅有效地避免了电荷注入效应引起的采样信号失真，而且消除了时钟馈通效应的不良影响。
The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed-through.
采样保持电路设计采用了电容下极板采样技术，不仅有效地避免了电荷注入效应引起的采样信号失真，而且消除了时钟馈通效应的不良影响。
The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed-through.
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