利用准循环ldpc码的结构特点，使用半并行结构的译码器可以实现复杂度和译码速率的有效折中。

According to the structure of Quasi-Cyclic LDPC code, we can make a trade-off between hardware complexity and decoding throughput by applying semi-parallel architecture.

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定义一个严格的序列，比如在瀑布模型中，与在并行工作中定义一个半排序的迭代序列是基本相同的。

Defining a strict sequence, as in a waterfall model, is just as much a process as defining a semi-ordered sequence of iterations in parallel work.

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本文提出了一种能实时完成二进制逻辑运算的光学并行处理系统，并给出了作为半加法器的实验结果。

A real time optical logic processor is presented, that can perform binary logic operations in parallel. Experimental result is given of the system as a half adder.

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