尽管ASIC的老利很低，但设计周期少、投没省用高、风夷较年夜，而可编程逻辑器件（Programmable Logical Device）设计活络、罪能强年夜，尤其非高密度现场可编程逻辑器件（Field Programmable Gate Array）其设计机能已完万可能与ASIC媲美，而且...
基于8个网页-相关网页
虽然 ASIC 的成本很低,但设计周期长、投入费用高、风险较大,而可编程逻辑器件(Programmable Logical Device,PLD)设计灵活、功能强大,尤其是高密度现场可编程逻辑器件(Field Programmable Gate ...
基于2个网页-相关网页
CPLD Complex Programmable Logical Device 可编程逻辑器件 ; 复杂可编程逻辑器件
programmable logical device pld 可编程逻辑器件
complex programmable logical device 复杂可编程器件
complicated programmable logical device 复杂可编程逻辑器件
in-system programmable logical device 在系统可编程逻辑器件
logical programmable device 可编程逻辑器件
The programmable logical device has big scale, quick working speed and is programmable which is extremely suitably used to realize DDS.
可编程逻辑器件具有器件规模大、工作速度快及可编程的硬件特点，非常适合用来实现DDS。
This paper mainly talks about designing the protocol layer of USB2.0 with the programmable logical device as the carrier through the VHDL language.
本文在此主要通过VHDL语言，利用可编程逻辑器件作为载体来设计usb2.0的协议处理层模块。
Based on a complicated programmable logical device (CPLD), a miniaturized universal pulse height analysis (PHA) module of high performance is realized.
介绍一种基于复杂可编程逻辑器件(CPLD)的通用高性能脉冲幅度分析(PHA)模块设计。
应用推荐