将「功能模拟（Function Simulation）阶段的模拟结果以及「逻辑闸层次模拟（Gate Level Simulation）阶段的模拟结果，比较他们之间的讯号输出与预期的结果在讯号的波形(Function及时序（Timing）…等方面是否相同。
基于4个网页-相关网页
conventional gate-level simulation [计] 传统的门级模拟
conventional gate level simulation 惯用闸位准模拟
gate level logic simulation [计] 门级逻辑模拟 ; 闸位准逻辑仿真
gate-level logic simulation 门级逻辑模拟
The design of MCS-51 Microcontroller is followed the Top-Down design way, including system partition coding (VHDL) RTL simulation synthesis, gate level simulation ect.
对MCS—51单片机进行正向设计，包括系统划分、编写代码、RTL级仿真与综合、门级仿真等。
GFMS is a Gate and Function Block of mixed-level simulation system, which is designed for experiment of Digital Logical.
GFMS是针对《数字逻辑》课程实验而设计的数学电路模拟系统。
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
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