The design of MCS-51 Microcontroller is followed the Top-Down design way, including system partition coding (VHDL) RTL simulation synthesis, gate level simulation ect.
对MCS—51单片机进行正向设计，包括系统划分、编写代码、RTL级仿真与综合、门级仿真等。
GFMS is a Gate and Function Block of mixed-level simulation system, which is designed for experiment of Digital Logical.
GFMS是针对《数字逻辑》课程实验而设计的数学电路模拟系统。
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
A new analytical model and some algorithms based on the conventional gate-level simulation are presented in this article.
本文在传统的门级逻辑模拟模型和算法的基础上引进了一些新概念，导出了一种新的分析模型和算法。
A new analytical model and some algorithms based on the conventional gate-level simulation are presented in this article.
本文在传统的门级逻辑模拟模型和算法的基础上引进了一些新概念，导出了一种新的分析模型和算法。
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