介绍了研究集成电路互连线电迁移的两种方法：加速寿命试验和移动速度试验。
Two main methods, accelerated lifetime test and drift velocity test, to study electromigration are described.
在一个集成电路中，多个芯片、共享内存以及互连形成了一个紧密集成的多处理核心(参见图4)。
On a single integrated circuit, multiple chips, Shared memory, and an interconnect form a tightly integrated core for multiprocessing (see Figure 4).
深亚微米集成电路的互连线延迟是设计中需十分重视并必须解决的问题。
Interconnect wire delay is a very important question that must to be resolved in deep submicron IC design.
问题可能出在器件的互连或工作在正常的时钟频率时集成电路就不能正常的运行了。
The problem might be an interaction between components or an IC that fails when run at normal operating clock rates.
垂直互连是三维微波和毫米波集成电路中的典型结构。
Vertical interconnections are typical structures in three dimensional microwave and millimeter wave integrated circuits.
本文首次利用时域有限差分(FDTD)法分析了高速集成电路芯片内半导体基片上的有耗互连传输线的电特性。
A full wave analysis of lossy interconnection lines on doped semiconductor substrates in high speed integrated circuits is carried out by means of a finite difference time domain (FDTD) approach.
本文对应用于超大规模集成电路光学互连的计算机产生的全息图(CGH)的量化及取样影响进行了分析。
The quantization and sampling effects of Computer Generated Hologram (CGH) for optical interconnection of very large scale integrated circuits are dis - cussed.
硅片上互连线几何变异提取对于超深亚微米工艺节点下集成电路可制造性设计研究开发极其关键。
Interconnect geometric variation extraction is a key factor for the integrated circuit design for manufacturability research and development, under ultra deep sub-micro process nodes.
在大量仿真数据以及当前集成电路设计工艺的基础上，提出了一种简单互连线负载的有效电容计算模型。
A simple and efficient model was presented for computing the effective capacitance of interconnect load based on simulation and integrated circuit process.
利用铜代替铝作为超大规模集成电路的互连接线，代表了半导体工业的重要转变。
Shift from al to Cu interconnects in Ultra-Large Scale Integrate (ULSI) is important for semiconductor industry.
论文介绍了互连参数的内容、受集成电路工艺变异的影响及定性方法；
The thesis introduced the interconnect parameters and the influence of process variations and the charactering method.
随着集成电路生产工艺的进展，互连线在集成电路设计中的影响越来越大。
With the development of IC process technology, the impact of interconnects on the design of IC's is becoming greater.
集成电路，一小片内含相互连接的微缩电路的半导体材料。
INTEGRATED circuit, a small piece of semiconductive material that contains interconnected miniaturized electronic circuits.
分析结果表明，该方法很适合高速集成电路芯片内互连线的计算机辅助分析。
The results show that this method is very fit for the computer aided analysis of on chip interconnects for the high speed VLSI.
本文提出了大规模集成电路中互连线的特征模型。
The characteristic model of interconnects in VLSI is proposed.
这种新型的硅基发光管结构在下一代集成电路中作为芯片之间或芯片内部的光互连具有非常广阔的应用前景。
The new type silicon-based luminous tube structure has a widely application prospect as light connection between chips or chips inner in next generation integrated circuit.
随着集成电路设计复杂性以及电路工作时钟频率的不断提高，互连与封装等寄生效应对电路的影响越来越大，产生了信号完整性问题。
At very high frequencies, interconnects and packages can only be characterized by a set of sampled data from measurements or electromagnetic simulations over the frequency of interests.
阐述了超大规模集成电路（ VLSI）特征尺寸的减小及互连线层数增加引起的互连线电容增加的问题。
The issue of interconnect capacitance rising from very large scale integration(VLSI)with a decreased feature size and increased number of wiring layers is described.
论文分析了当前的研究状况，介绍了集成电路工艺变异的内容及对集成电路器件、互连以及电路性能的影响。
This thesis analyzed the current researching situation, introduced process variations and the influence to IC devices, interconnect and circuits.
随着集成电路特征尺寸的不断减小，互连线的串扰噪声对工艺波动的灵敏度也在相应增加。
As the IC feature size continues to decrease, interconnect cross-talk noise with the process fluctuation is also a corresponding increase in sensitivity.
因此在集成电路设计中，互连工艺波动对集成电路性能的影响变得至关重要。
So the impact of process fluctuations on performance has become extremely critical in IC design.
形成穿过掩埋绝缘层的互连结构，以连接集成电感器和集成电路。
An interconnection structure is formed through the buried insulating layer to connect the integrated inductor to the integrated circuit.
形成穿过掩埋绝缘层的互连结构，以连接集成电感器和集成电路。
An interconnection structure is formed through the buried insulating layer to connect the integrated inductor to the integrated circuit.
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