存储单元和数据线用复位信号来控制，以使数据可在该半导体器件中被可靠地输出。
A memory cell and a data line are controlled with a reset signal, so that data can be reliably outputted in the semiconductor device.
当选择并且连接到用来读取的读取电路时，取消位线的复位状态并且通过所选的位线读取存储在所选存储器单元中的信息。
The reset state of a bit line is canceled when selected and connected to a read circuit for read, and information stored in a selected memory cell is read via the selected bit line.
本论文的嵌入式硬件环境，包括CPU的外围时钟电路，复位电路，存储器单元，LCD模块，触摸屏，键盘，FLASH，SDRAM，网络接口等部分。
The embedded system in this thesis include CPU , memory part , LCD part, touching screen, keyboard, FLASH, SDRAM and internet interface and so on.
分别在驾驶室各处安装报警延伸复位按钮盒4套，敷设电缆线并接线，由接线箱或主控单元至各延伸报警复位按钮盒电缆，共计：电缆四条。
Mount remote reset unit (4 PCS) in different places on the bridge and laying cable (2 core, 4 PCS) from remote reset unit to main control unit or junction box.
文中论述了混合级综合、综合中的功能单元库等问题；提出分辨信号、断言语句应该综合，并给出了综合分辨信号、断言语句的方法；还给出了高级综合中复位信号和时钟信号的处理方法。
The new viewpoints that assertion statement and resolved signal in VHDL should be synthesized are advanced, and the methods to synthesis assertion statement and resolved signal are presented.
文中论述了混合级综合、综合中的功能单元库等问题；提出分辨信号、断言语句应该综合，并给出了综合分辨信号、断言语句的方法；还给出了高级综合中复位信号和时钟信号的处理方法。
The new viewpoints that assertion statement and resolved signal in VHDL should be synthesized are advanced, and the methods to synthesis assertion statement and resolved signal are presented.
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