This paper introduces the design and realization of a high-speed and low-cost virtual logic analyzer based on FPGA and USB2.0 bus.
本文介绍了一种基于FPGA的USB2.0高速、低成本的虚拟逻辑分析仪的设计原理与实现方法。
Moreover, the logic analyzer-based software environment helps each user customize the views according to his or her own test needs.
此外，基于软件环境的逻辑分析仪可帮助每个用户根据他们自己的测试需求进行定制。
On the basis of above mentioned, this thesis discusses the research and design of virtual logic analyzer based on the full use of FPGA technology and virtual instrument technology.
正是基于此，本文充分运用FPGA技术和虚拟仪器技术，开展了虚拟逻辑分析仪系统的研究与设计。
The topic—the Design of GPIB Interface Chip and application In Logic analyzer has two main parts: The first part is the design of GPIB interface board based on CPLD;
本课题—GPIB接口芯片的设计及在逻辑分析仪中的应用研究主要有两个部分：第一部分是基于CPLD的GPIB接口板设计；
The topic—the Design of GPIB Interface Chip and application In Logic analyzer has two main parts: The first part is the design of GPIB interface board based on CPLD;
本课题—GPIB接口芯片的设计及在逻辑分析仪中的应用研究主要有两个部分：第一部分是基于CPLD的GPIB接口板设计；
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