• 系统总体设计思想闪速存储器特点阐述

    The system's general design idea and the features of the flash memory are represented in the paper.

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  • 高压发生系统用来闪速存储器编程除操作时提供高压。

    High voltage system is used to generate high voltage for Flash Memory when programming and erasing.

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  • 通过实验研究存储器存储单元应力诱生电流(ILC)产生机理

    The generation mechanism of stress induced leakage current (SILC) in flash memory cell is studied by experiments.

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  • 为了现有条件下进一步降低存储器单位成本开发了各种单管多位技术

    To reduce bit cost in the same generation of process, multi-bit in one cell technology has been developed for flash memory.

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  • 除了建构自己处理器装备手机三星闪速存储器顶尖供应商将其应用自己的和其他竞争对手手机上。

    In addition to building the processors that power its phones, Samsung is also among the leading suppliers of flash memory used in its handsets, as well as those of competitors.

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  • 本文介绍了闪速存储器结构特点工艺技术EPROM和EEP - ROM电路进行了比较

    This paper introduces the FLASH MEMORY circuits technique and structure characteristic, also compared the circuits with that of EPROM and EEPROM.

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  • 本发明实施例方案存储器芯片上实现了闪速存储器功能导入只读存储器功能,降低成本。

    The embodiment of the invention realizes the functions of the flash memory and a read only memory on a chip of the flash memory, and the cost is reduced.

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  • 其中图像摄取部分采用CPLD控制CMOS图像传感器采集图像,把图像数据存入容量闪速存储器

    Use CPLD to control the CMOS image sensor and the flash storage memory to record the image in the image record part.

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  • 此外,威廉姆斯苹果大量幕后工作例如与海力士(Hynix)等供应商签订协议预付约12.5亿美元的订金购买闪速存储器此举Nano音乐播放器的推出大有帮助

    Williams has done a lot for Apple, all of it behind the scenes, such as his work on a deal to prepay suppliers like Hynix some $1.25 billion for flash memory, a move that helped Apple launch the Nano.

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  • 改进的基于闪速EEPROM存储器存储子系统包括多个阵列一个都带有两个数据寄存器一个控制器电路

    An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with a duplicity of data registers and a controller circuit.

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  • 改进的基于闪速EEPROM存储器存储子系统包括多个阵列一个都带有两个数据寄存器一个控制器电路

    An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with a duplicity of data registers and a controller circuit.

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