所用的电路为蔡氏电路和锁相环电路。
数字锁相环是数字解调器的关键部件。
Digital phase lock loop is a key part of the digital demodulator.
锁相环在很多领域都得到了广泛应用。
利用锁相环完成了码速恢复。
提出一种改进的双控制通路锁相环结构。
The authors propose an improved phased locked loop (PLL) architecture with dual control paths.
锁相环电路，相移方法，及集成电路芯片。
Phase-locking loop circuit, phase shifting method, and IC chip.
本文研究了电荷泵锁相环电路的模型和电路设计。
This dissertation presents a study on modeling and circuit design of Charge Pump Phase-Locked Loops.
提出了一种具有自动变模控制的快速全数字锁相环。
A fast all digital phase-locked loop with automatic modulus control is presented.
在本文中，我们将展现一个新的锁相环锁定检测方法。
In this paper, a new method of PLL lock detector will be presented.
这个数据分离器的主要部分是一个数模混合的锁相环。
A digital-analog PLL is the main part of the data separator.
本文研究了锁相环的基本结构与系统构架及其性能优劣。
In this thesis the basic architecture and the performance evaluation of phase-locked loop are presented.
对如何提高嵌入式全数字锁相环的锁定速度进行了研究。
How to raise the phase lock speed of embedded DPLL is researched.
本文还对相干载波提取中的锁相环提出了一种改进方法。
It also give an improved method for PLL (phase locked loop) to extract coherent carrier.
在通信领域中，锁相环频率合成器起着越来越重要的角色。
In the field of communications, PLL synthesizers playing an increasingly important role.
在锁相环频率合成器中，双模前置分频器是一个速度瓶颈。
In PLL frequency synthesizers, dual modulus prescaler is a bottleneck in achieving a higher operation speed.
为了尽量减少抖动的锁相环，建议，以避免在测试输出的积极信号。
In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.
根据锁相环的原理，使用反射式光电传感器实现了系统的颜色识别。
According to the theory of phase-locked loop, we use reflected photoelectric sensor to carry out the color recognition.
该锁相环由计算频率误差、更新环路中间变量、输出控制信号组成。
The SPLL consists of calculation frequency error, updating loop middle variable, and output control signal.
本文叙述了一个用微机控制的锁相环频率合成数字调谐系统的原理和设计。
In this paper the principle and design of a microcomputer-controlled PLL frequency synthesis digit tuning system is discussed.
本文主要研究了基于全数字锁相环的谐振型逆变器频率跟踪的数字化控制方案。
The paper studies digital control scheme of resonance inverter frequency-tracking based on all digital phase-locked loop.
在我们准备为锁相环找到最优配置之前，首先要考虑如何找到锁相环的所有配置。
Before we can setout to find the optimal configuration for our PLL, we need to first consider how we find any configuration for our PLL.
本文介绍了一种利用混合数字锁相环(HDPLL)实现码元定时恢复的新方法。
Anovel approach to implement symbol timing recovery is presented which USES a hybrid digital phase locked loop (HDPLL).
本机工作在UHF频率，采用PLL锁相环电路，预设256个可选择使用频率。
This system works on UHF frequency brand, use PLL circuit. There are 256 frequencies for your option.
然后介绍了锁相环(PLL)的基本结构、相位模型、频率响应、噪声及杂散性能。
Then presented the basic structure, phase model, frequency response and performance analysis for noise and spur, of phase locked loop (PLL).
分析了锁相环的基本原理和实现，并对射频电路设计理论和阻抗匹配问题进行了探究。
Analyzing the basic theory and development of PLL, and studying the design theory and impedance match problem of experimental circuit board.
对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。
The digital realization of monostable circuit and extraction of bit-synchronous signal with digital phase lock loop are also introduced in detail.
该方案利用信号自身的特性，采用数字逻辑设计，有效避免了性能不高的锁相环的使用。
In the new scheme proposed, the phase lock loop is avoided and the digital logical circuit is used.
采用高精度的直接数字频率合成（DDS）和数字锁相环技术，实现了高频率跟踪精度。
DDS and digital phrase-lock technology have been applied in FPGA to improve the accuracy of frequency tracking.
以数字延迟锁相环为基础，并采用数模混合技术，实现了带电源控制的数字延迟锁相环。
Based on digital delay-locked loop, the mix signal technique is used to implement the digital delay locked loop with the resource control technique.
以数字延迟锁相环为基础，并采用数模混合技术，实现了带电源控制的数字延迟锁相环。
Based on digital delay-locked loop, the mix signal technique is used to implement the digital delay locked loop with the resource control technique.
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