本发明涉及一种锁存器及液晶显示源极驱动装置。
The invention relates to a flip latch and a liquid crystal display source drive device.
比较器是前置放大器与动态锁存器组成的开关电容电路。
It is a switch capacitor circuit which consists of the preamplifier and dynamic latch.
同时，合并两个锁存器的跟踪差分对可以减小分频器的功耗。
The power of divider can be declined by means of combination of the trace differential pairs of these two latches.
该比较器包含一级预放大器、动态锁存器及时钟控制反相器。
The comparator includes a preamplifier, a dynamic latch and a clocked inverter.
负载时钟(372)施加到将图案加载到所述多个锁存器装置中。
A load clock (372) is applied to load a pattern into the plurality of latch devices.
在当前发布的源程序中描述的寄存器或锁存器不符你描述的风格。
The description style you are using to describe a register or latch is not supported in the current software release.
此设置的唯一问题是我们需要8个IO口来控制每个锁存器的CP线。
The only problem with this setup is that we need 8 IO lines to control the CP line for each latch.
所述动态锁存器适于至少部分基于输入数据信号产生放大的输出数据信号。
The dynamic latch is adapted to generate an amplified output data signal based at least in part on the input data signal.
文中主要讨论常用时序逻辑模型(D锁存器、D触发器和T触发器)的建立。
This article mainly discusses the building of such sequence logic models as D_latch, D_FF and T_FF.
尽管期望这种集成电路作为一种锁存器电路，它也可以当作推荐的标准触发器。
Even though this IC is supposed to work as a latch circuit, it can also be made to function as RS (recommended standard) flip-flop.
尽管期望这种集成电路作为一种锁存器电路，它也可以当作推荐的标准触发器。
Even though this IC (integrated circuit) is supposed to work as a latch circuit, it can also be made to function as RS (recommended standard) flip-flop.
因为下面进行了简化，单“阀门”装置将由一套比较器和一个RS锁存器代替。
For simplification below, a single "threshold" device will be replaced by a set of comparators and a rs Latch.
该音响系统是依赖于四和八进制锁存器IC的，因此它不会映射到CPU的直接…
The sound system is tied to quad and octal-latch IC's, so is not mapped to the CPU directly…
译码电路接收测量端模拟信号，转化为7段显示的数字信号，发送到数据锁存器上。
The A/D decoding circuit received simulation signal form measurement port and converted the signals into data signals which displayed by 7-segment, then signals were sent to data latch.
通过分离跟踪差分对与交叉耦合对，并减小后者的偏置电流可以提高锁存器的工作速度。
The speed of latch has a direct effect on the performance of divider, which can be improved by separating trace differential pair and cross-coupled pair and decreasing the bias current of the later.
缓冲区的获取是通过使用锁存器（latch）和锁访问信息来管理的，该锁存器称作 mutex。
Buffer acquisition is managed through the use of latches, known as mutex, and lock-access information.
在一些实施例中，所述电平位移电路包括锁存经转换的输出信号的电平位移锁存器(208)。
In some embodiments, the level shifting circuit includes a level shifting latch (208) that latches a translated output signal.
他们将利用纳米成型法(NMT)，融合了塑料对金属的腐蚀，不再需要各种附件锁存器或插槽。
They will make use of the Nano Molding Method (NMT) that fuses the plastic against the etched metal, removing the need for various attachment latches or slots.
具体电路由锁存器、选择器及分频器组成，以CM O S逻辑和源极耦合逻辑(SCL)实现。
The concrete circuits are composed of latches, selectors and frequency dividers. They are implemented with CMOS logic and source coupled logic (SCL).
在实施例中，所述系统包含第一锁存器和经耦合以将时序信号提供给所述第一锁存器的脉冲产生器。
In an embodiment, the system includes a first latch and a pulse generator coupled to provide a timing signal to the first latch.
存储器采用六管CMOS存储单元、锁存器型敏感放大器和高速译码电路，以期达到最快的存取时间。
A fast access time is achieved by using six-transistor CMOS memory cell, latched sense amplifier, and high-speed decoder circuit.
为了使电路性能达到低电压、低功耗与超高速的统一，本文采用一种改进型共栅结构的动态负载锁存器。
In order to achieve the unification of low voltage, low power and super high speed, the article applies an improved common-gate structure dynamic load latch.
所述选择器输入经确认以使得所述图案的推导图被所述多个选择器接收，且返回到所述多个锁存器装置。
The selector input is asserted such that a derivative of the pattern is received by the plurality of selectors and returned to the plurality of latch devices.
系统时钟(371)施加到所述多个锁存器装置，使所述图案的所述推导图加载到所述多个锁存器装置中。
A system clock (371) is applied to the plurality of latch devices such that the derivative of the pattern is loaded into the plurality of latch devices.
为了克服现有等价性验证技术中难以精确匹配锁存器的局限性，提出了一种结合多种方法的新型锁存器匹配算法。
A novel latch mapping technique for equivalence checking was proposed to overcome the limit of low accuracy of previous mapping methods.
一种用于确定存储在PROM中数据的完整性的方法和设备，其中PROM配置了至少一个连接到两组块的保持锁存器。
A method and apparatus for determining the integrity of data stored in a PROM device provides at least one holding latch connected to two sets of blocks.
所述数字部分可包含多个锁存器装置（361到364），且所述模拟部分可 包含多个存储单元（321）和多个选择器装置（325）。
The digital portion may include a plurality of latch devices (361-364), and the analog portion may include a plurality of memory cells (321) and a plurality of selector devices (325).
在一些实施例中，接收机锁存器电路包括动态锁存器，该动态锁存器具有至少一个用于接收输入数据信号的输入端子和至少一个锁存器端子。
In some embodiments, a receiver latch circuit, includes a dynamic latch having at least one input terminal to receive an input data signal and at least one latch terminal.
所述动态锁存器包括至少一个耦合在所述至少一个输入端子和所述至少一个锁存器端子之间的电容器，以减少所述输入数据信号中的码间干扰。
The dynamic latch includes at least one capacitor, coupled between the at least one input terminal and the at least one latch terminal, to reduce intersymbol interference in the input data signal.
双回转机构的步进电机控制电路由TDA1521音频集成功率放大器组成平衡桥式功率驱动电路，由计算机并行口经过锁存器构成脉冲分配器。
To control stepping motors, the balance bridge power drive circuit is made up by TDA1521 integrated audio power amplifier, the pulse allotter is made up by the parallel ports of computer and latches.
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