提供了用于防止固件缺陷干扰逻辑时钟的计算机实现的方法和数据处理系统。
A computer implemented method and data processing system are provided for preventing firmware defects from disrupting logic clocks.
该文讨论了几种逻辑时钟系统和并行及分布式监测系统MS - 1中的物理时钟，并比较了它们的优缺点。
This article discusses several kinds of logical time systems, and also discusses the physical time system in our parallel and distributed monitor system MS-1.
首先讨论了逻辑时钟方法及逻辑时钟的修改算法，然后介绍了自行研制的分布式s4系统中逻辑时钟监控器模块的实现方法。
Firstly it discusses the approach of logical clock and revise algorithm of logical clock, then introduces the implementation approach of logical time monitor module in distributed S4 system.
“激光脉冲轻拍壳层产生了像铃声一样声音”，国家标准和技术研究所的物理学家Till Rosenband说，现有的量子逻辑时钟是由他开发的。
"With a laser pulse, you can tap that shell and make it ring like a bell," said physicist Till Rosenband of NIST, who built the existing quantum-logic clock.
按照逻辑芯片设计特点，将芯片工作时的信号分为4种：时钟信号、输入信号、组合输出信号和寄存器输出信号。
According to the logic chip design feature, the chip work's time signal can be divided into 4 kinds: clock signal, input signal, combination output signal and register output signal.
在突发式的接收模块中，逻辑电平的恢复和时钟数据的恢复是其关键的问题。
The most difficult problem in burst mode receiver would be signal logic level recovery and data and clock recovery.
整个设计采用VHDL语言描述，经过逻辑优化，该显示控制器有着比同类控制器占用资源少、时钟延迟小等优点。
The whole design is described in VHDL. By logic optimization, the controller has an advantage of less resource utilization and less clock delay compared with other similar controllers.
在一个数据锁存如果LE是低，时钟是在高或低的逻辑电平举行。
The a data is latched if le is low and clock is held at a high or low logic level.
在各单元中包括寄存器，各寄存器与时钟脉冲同步，依次取得逻辑运算结果并加以保存。
Each cell contains a register. Each register successively acquires logic calculation results in synchronization with a clock and maintains them.
逻辑控制电路设计：D触发器、不重叠时钟脉冲发生器等模块的设计。
Logical control circuit design: this part includes the design of DFF, non-overlap clock generate and so on.
处理器包含一个时钟，一条指令控制单元，一个算术和逻辑单元，并登记。
The processor contains a clock, an instruction control unit, an arithmetic and logic unit, and registers.
从消除时钟冗余，提高时钟利用率以达到降低功耗的思想出发，提出基于双边沿触发的触发器的逻辑设计。
To erase redundancy of the clock, improve clock utilization rate and reduce power dissipation, this paper proposes the logic design of low power flip-flop based on double edge trigger.
他由一个8位6502CPU（不支持整数模式，也被称为BCD），DMA传输单元，伪音频处理单元，1/12时钟分频器，以及1位逻辑单位的地址译码。
It consists of an 8-bit 6502 CPU (without support for decimal mode, also known as BCD), DMA transfer unit, pseudo audio processing unit, 1/12 clock divider, and a bit of logic for address decoding.
在一M 68300家庭组成部分，其主要职能和胶合逻辑都是正确连接国内，以相同的时钟定时，全面测试，并统一记录。
In an M68300 family component, the major functions and glue logic are all properly connected internally, timed with the same clock, fully tested, and uniformly documented.
使用时钟作为资料在定时关闭已经创造各式各样的问题，特别在逻辑和物理综合。
Using clock as data has created various issues in timing closure, particularly in logic and physical synthesis.
模拟结果表明所设计的触发器具有正确的逻辑功能，跟传统的时钟低摆幅双边沿触发器相比，降低近17%的功耗。
The results of simulation suggest that the designed FK-LSCDFF has correct logic function, and reduces 17% powedissipation compared with conventional low-swing clock double-edge-triggered flip-flop.
时钟信号控制着数字系统的操作，它让逻辑门计算新的结果，然后由触发器存储执行结果。
Clock regulate the operation of a digital system by allowing time for new results to be calculated by logic gates and then capturing the results in flip-flops.
提出了一种新的时钟偏斜规划算法，该算法所生成的时序约束可以有效地促进逻辑综合工具的面积优化。
A new clock skew scheduling algorithm is proposed. This algorithm generates timing constraints which can effectively promote the area optimization of logic syn thesis.
之前看的那些顺序逻辑的例子好像确实全都没有时钟信号。
For sequential logic, the key is clock. Everything has to be synchronized with clock.
被禁用的模块中包含的相关逻辑和时钟树会因此停止消耗能量。
Associated logic and clock trees contained in a disabled module will therefore stop consuming power.
计时器A的时钟源可来自时钟A或B，它们可以通过逻辑与形成多种组合。
The clock source of Timer A is from clock source A and clock source B which are ANDED to form varieties of combinations.
计时器A的时钟源可来自时钟A或B，它们可以通过逻辑与形成多种组合。
The clock source of Timer A is from clock source A and clock source B which are ANDED to form varieties of combinations.
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