用VHDL（甚高速集成电路硬件描述语言）有限状态机设计了数据采集时序的控制电路。

The sequence control circuit of DATA collection is designed with finite state machine(FSM) of VHDL.

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用高速的FPGA代替ECL集成电路制作了北京谱仪的主触发电路，其设计过程中使用了硬件描述语言VHDL，得到了和原电路同样的性能，但增加了灵活性。

Master Trigger Controller was made using fast FPGA instead of ECLIC. VHDL was used in its design. The same performance was obtained with increased flexibility. .

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