This paper gives a design of high AD sampling based on FPGA,the high sampling clock based on FPGA and the configured chips of AD95164 and ADC by FPGA. Effective Number Of Bits（ENOB） of the sampling result are measured.
本文提出基于FPGA的高速AD采样设计,给出了基于FPGA的高速采样时钟设计方案以及FPGA对时钟芯片AD95164与ADC的配置设置,并对采样结果有效位数进行测定。
参考来源 - 基于FPGA的高速AD采样设计·2,447,543篇论文数据，部分数据来源于NoteExpress
该方法可用于软盘驱动器或高速采样的接口设计。
This method can be used to design the interface of a floppy disk driver or a highspeed sampling circuit.
并设计了先对回波信号进行高速采样然后同步累加进行脉冲积累的方案。
The according pulse accumulation method is designed and realized, i. e. digitalizing the echo and synchronously accumulating them in RAM.
传统的图像或视频信息获取过程是先进行高速采样，然后再进行信号压缩。
In the conventional image or video signal acquisition progress, we need to sample at a high rate first, and then compress the signal.
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