...术逻辑单元ALU(ArithmeticLogic Unit)、 一个桶式移位器(BarrelShifter)、一个乘法器(Multiplier)、一个除法器(Divider) 和一个测试模块(TestU11it)。 6.指令译码器单元(IDU) 指令译码器的主要职责是从指令预取队列中取出指令,并进行两级译码。
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In the quantization module, a custom divider is used to reduce the division operation time.
在量化模块中采用了自行实现的除法器,减少了除法运算的时间。
参考来源 - 基于DE2平台的JPEG编码器设计This paper describes in detail how to design the multiplier and divider during the course of implementing RS(256,252)decoder . These two components have regular structure and can be easily realized on VLSI chips.
详细介绍了在设计 RS( 2 5 6,2 5 2 )译码器过程中所用的乘法器和除法器 ,两种器件具有规则的结构 ,有利于用 VLSI硬件电路来实现。
参考来源 - RS(256·2,447,543篇论文数据,部分数据来源于NoteExpress
介绍了用FPGA实现先行进位单元阵列除法器的原理及方法。
The theory and method of precedent cellular arrays divider by means of FPGA are introduced.
本文介绍了一种用声光调制器、模拟除法器和自动锁相放大器来改进激光探针测试系统稳定性的方法。
This paper reports a technique used lor improving the stability of the laser probe consisting of an acoustooptic modulator, an analogue divider and an auto-lock-in amplifier.
为提高除法计算的速度,提出了新的基-16算法的高速除法器算法,并以专用集成电路设计方法实现。
In order to improve the speed of division, a novel algorithm of radix-16 high speed divider and its ASIC implementation are presented.
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