芯片规模不断增加、设计门数不断增长，验证已成为芯片开发的主要瓶颈。

With the continuing increase in chip scale and design gates, verification has become the main bottleneck in chip development.

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所以一个基于ERCCL的系统可以大大减少逻辑门数，从而降低系统能耗。

The gate count of a system based on ERCCL can be significantly reduced, which, in turn, will decrease the energy loss.

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实验结果表明，该实现方法比原算法降低65%的功耗，等效门数减少13%。

Experimental result shows that, this implementation method compared with the original algorithm, the consumption reduces by 65%, and equivalent door number reduces by 13%.

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So what are the expectations over the course of these few weeks?

那么短短数周,在这门课上你们需要做的是什么？

哈佛公开课 - 计算机科学课程节选