本实用新型由时基信号电路、数字钟电路，时间显示屏，半导体存贮器，编程电路及执行电路组成。

The utility model is composed of a time signal circuit, a digital clock circuit, a time display screen, a semiconductor memory, a programming circuit and an executing circuit.

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两位研究者就可以以10的16次方分之一的精度反复核对时间，这证明这样的原子钟可以通过电学和光学电路连接起来。

The two researchers were able to cross-check the time to an accuracy of one in 1016, an exercise proving that such clocks can be interlinked over electronic and optical circuits.

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介绍了利用VHDL硬件描述语言结合FPGA可编程器件进行数字钟的设计，并通过数码管驱动电路动态显示计时结果。

The paper introduces the design of digital clock based on FPGA and VHDL, the time of clock can be displayed with the digital driving circuit.

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