介绍了VHDL逻辑级模拟系统中模拟模块的设计和实现。
This paper presents design and implementation of the simulation module in a logic-level VHDL simulation system.
本文介绍了一种将MOS电路级描述转换成逻辑级描述的统一方法。
An unified method for converting MOS circuit level description into logic level description is presented.
面向逻辑级描述的同步时序电路，以触发器为核的电路划分算法BWFSF将电路划分为大功能块。
BWFSF algorithm partition synchronous sequential circuit to many big function blocks by backward width-first search with fli.
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